Abstract: The present invention relates to the generation of display identification (ID) information in a computer display system. The display ID generator includes a memory which stores display ID information. A control logic device couples the information from the memory to a first FIFO. A state machine accesses the information held in the first FIFO and determines the duration information. Next, the state machine couples the information to a second FIFO. Last, the information in the second FIFO is coupled to a third memory and a sequential counter. After initial loading of information in second memory and sequential counter, the sequential counter determines when second memory and itself will be loaded with the next set of information. Once the sequential counter reaches zero, it generates a signal enabling itself and the second memory to load the next set of information.

Abstract: An apparatus and a method of generating video timing information and display ID information wherein the video timing generator includes a memory, typically a random access memory, which stores video timing information. A control logic device couples the information from memory to a FIFO. The control device further couples the initial information from the FIFO to a second memory, typically a register, and a sequential counter. After initial loading of information in the second memory and sequential counter, the sequential counter determines when the second memory and itself will be loaded with the next set of information. Once the sequential counter reaches zero, it generates a signal enabling itself and the second memory to load the next set of information. The display ID generator includes a memory which stores display ID information. A control logic device couples the information from the memory to a first FIFO.

Abstract: A cursor generator for use in a computer system having a high pixel clock rate. The cursor generator includes a first memory which stores a line of the cursor for display on the display device and a second memory which stores the entire cursor. The data for the line of the cursor can be more quickly retrieved from the first memory than from the second memory, and the first memory is clocked under the control of the high pixel clock rate while the second memory is clocked at a slower clock rate. A controller couples data for the one line of the cursor from the second memory, which is typically dynamic random access memory to the first memory which is typically a high speed register or a combination of registers and multiplexors. The controller couples the data for one line at a time of the cursor to the display device in order to display the cursor in conjunction with the rest of time image displayed on the display device.

Abstract: A system for processing of data wherein the data is inputted over time into the system such that a second packet of data is inputted before a first packet of data, the system comprising a first processor coupled to a second processor, the first processor operating on only the first packet of data and the second processor operating on only the second packet of data.