Abstract: A host module configured for insertion into a chassis of a network element includes a Printed Circuit Board (PCB); a plurality of rails disposed on the PCB, for housing one or more universal sub slot modules on the host module, wherein the plurality of rails are for guiding a universal sub slot module during insertion and for stabilization thereof; and a faceplate disposed to the PCB and including one or more openings each for the one or more universal sub slot modules, wherein the PCB communicates to each of the one or more universal sub slot modules via a plurality of high-speed links that are at least 28 Gbps each. At least one of the one or more universal sub slot modules can be a coherent modem or a router.

Abstract: Systems and methods include receiving an Optical Transport Network (OTN) signal; segmenting the OTN signal into one or more flows of packets; and transmitting the one or more flows of packets spread over one or more Ethernet links. The one or more flows can be transmitted over a Leaf/Spine network, and the one or more flows can be elephant and/or mice flows.

Abstract: A universal sub slot module includes a Printed Circuit Board (PCB) including circuitry for power, a data plane, and a control plane; a faceplate connected to one end of the PCB and connectors connected to another end of the PCB, wherein the connectors are configured to connect to corresponding connectors in a host module; and a form factor containing the PCB and configured to interface a sub slot in the host module configured to operate in a chassis-based or rack mounted unit network element. The host module can include a plurality of sub slots, each being a port having one of the universal sub slot module and a filler module. The data plane can be configured to implement one of Optical Transport Network (OTN), Beyond 100G, Flexible Optical (FlexO), Ethernet, and Flexible Ethernet (FlexE).

Abstract: A network element (16) includes ingress optics (22) configured to receive a client signal; egress optics (30) configured to transmit packets over one or more Ethernet links (20) in a network (12); circuitry (26, 28) interconnecting the ingress optics (22) and the egress optics (30), wherein the circuitry is configured to segment an Optical Transport Network (OTN) signal from the client signal into one or more flows; and provide the one or more flows to the egress optics for transmission over the one or more of Ethernet links (20) to a second network element (18) that is configured to provide the one or more flows into the OTN signal.

Abstract: A module for use in a hardware platform for networking, computing, and/or storage includes a printed circuit board assembly having a primary side and a secondary side, wherein the primary side includes more physical space, in a vertical direction extending out from the printed circuit board assembly, than the secondary side; electrical and/or optical components disposed on the primary side of the printed circuit board assembly; and a secondary side heatsink located on and extending from the secondary side, wherein the secondary side heatsink is disposed to one of i) an electrical and/or optical component disposed on the secondary side, and ii) an optical component disposed on the primary side, for thermal management.

Abstract: A network element (16) includes ingress optics (22) configured to receive a client signal; egress optics (30) configured to transmit packets over one or more Ethernet links (20) in a network (12); circuitry (26, 28) interconnecting the ingress optics (22) and the egress optics (30), wherein the circuitry is configured to segment an Optical Transport Network (OTN) signal from the client signal into one or more flows; and provide the one or more flows to the egress optics for transmission over the one or more of Ethernet links (20) to a second network element (18) that is configured to provide the one or more flows into the OTN signal.

Abstract: Time transfer systems and methods implemented in a first node steps of communicating a stream of encoded blocks with a second node; and communicating synchronization messages with the second node via a synchronization message channel in overhead associated with the stream of encoded blocks, wherein the synchronization messages are utilized for synchronization of a clock at the second node. Each block in the stream of encoded blocks can be one of a data block and an overhead block.

Abstract: A universal sub slot module includes a Printed Circuit Board (PCB) including circuitry for power, a data plane, and a control plane; a faceplate connected to one end of the PCB and connectors connected to another end of the PCB, wherein the connectors are configured to connect to corresponding connectors in a host module; and a form factor containing the PCB and configured to interface a sub slot in the host module configured to operate in a chassis-based or rack mounted unit network element. The host module can include a plurality of sub slots, each being a port having one of the universal sub slot module and a filler module. The data plane can be configured to implement one of Optical Transport Network (OTN), Beyond 100G, Flexible Optical (FlexO), Ethernet, and Flexible Ethernet (FlexE).

Abstract: A universal sub slot module is configured to be inserted in a slot in a hardware module that is configured to be inserted in one of a chassis and rack mounted unit. The universal sub slot module includes a printed circuit board; an optics component on the printed circuit board; a data plane and a control plane on the printed circuit board and communicatively coupled to the optics components; and connectors on the printed circuit board and communicatively coupled to the data plane and the control plane, wherein the connectors are configured to connect to corresponding connectors in the one or more hardware modules.

Abstract: A module for use in a hardware platform for networking, computing, and/or storage includes a printed circuit board assembly having a primary side and a secondary side, wherein the primary side includes more physical space, in a vertical direction extending out from the printed circuit board assembly, than the secondary side; electrical and/or optical components disposed on the primary side of the printed circuit board assembly; and a secondary side heatsink located on and extending from the secondary side, wherein the secondary side heatsink is disposed to one of i) an electrical and/or optical component disposed on the secondary side, and ii) an optical component disposed on the primary side, for thermal management.

Abstract: A module for use in a hardware platform for networking, computing, and/or storage includes a printed circuit board assembly having a primary side and a secondary side, wherein the primary side includes more physical space, in a vertical direction extending out from the printed circuit board assembly, than the secondary side; electrical and/or optical components disposed on the primary side of the printed circuit board assembly; and a secondary side heatsink located on and extending from the secondary side, wherein the secondary side heatsink is disposed to one of i) an electrical and/or optical component disposed on the secondary side, and ii) an optical component disposed on the primary side, for thermal management.

Abstract: A universal sub slot module is configured to be inserted in a slot in a hardware module that is configured to be inserted in one of a chassis and rack mounted unit. The universal sub slot module includes a printed circuit board; an optics component on the printed circuit board; a data plane and a control plane on the printed circuit board and communicatively coupled to the optics components; and connectors on the printed circuit board and communicatively coupled to the data plane and the control plane, wherein the connectors are configured to connect to corresponding connectors in the one or more hardware modules.

Abstract: A network element includes ingress optics configured to receive a client signal; egress optics configured to transmit packets over one or more Ethernet links in a network; circuitry interconnecting the ingress optics and the egress optics, wherein the circuitry is configured to segment an Optical Transport Network (OTN) signal from the client signal into one or more flows; and provide the one or more flows to the egress optics for transmission over the one or more of Ethernet links to a second network element that is configured to provide the one or more flows into the OTN signal.

Abstract: Time transfer systems and methods implemented in a first node steps of communicating a stream of encoded blocks with a second node; and communicating synchronization messages with the second node via a synchronization message channel in overhead associated with the stream of encoded blocks, wherein the synchronization messages are utilized for synchronization of a clock at the second node. Each block in the stream of encoded blocks can be one of a data block and an overhead block.

Abstract: Time transfer systems and methods in Flexible Ethernet (FlexE) include, in a node supporting Flexible Ethernet (FlexE), communicating a FlexE group with an adjacent node via a FlexE shim; providing a synchronization message channel to the adjacent node via overhead of the FlexE shim for the FlexE group; and exchanging synchronization messages via the synchronization message channel with the adjacent node. The synchronization messages can be Precision Time Protocol (PTP) messages. A timestamp point for a synchronization message can be a start of a FlexE frame or multi-frame boundary.

Abstract: An active device lid for a device base. The device lid includes a heatsink proximate to a circuit assembly and configured to remove heat generated by the device base, the circuit assembly configured to generate an operating signal voltage for the device base, and a connector configured to connect the circuit assembly to the device base, where the device base is configured to connect to a device mounting substrate on a substrate side of the device base, and where the circuit assembly is configured to be at least partially located on an opposing side of the device base, the opposing side opposing the substrate side.

Abstract: Time transfer systems and methods in Flexible Ethernet (FlexE) include, in a node supporting Flexible Ethernet (FlexE), communicating a FlexE group with an adjacent node via a FlexE shim; providing a synchronization message channel to the adjacent node via overhead of the FlexE shim for the FlexE group; and exchanging synchronization messages via the synchronization message channel with the adjacent node. The synchronization messages can be Precision Time Protocol (PTP) messages. A timestamp point for a synchronization message can be a start of a FlexE frame or multi-frame boundary.

Abstract: Time transfer systems and methods in Flexible Ethernet (FlexE) between a first node and a second node include detecting a timestamp point of reference in FlexE overhead and sampling a time based thereon; communicating samples of the timestamp point of reference between the first node and the second node; and determining a time delay between the first node and the second node based on the samples.

Abstract: An active device lid for a device base. The device lid includes a heatsink proximate to a circuit assembly and configured to remove heat generated by the device base, the circuit assembly configured to generate an operating signal voltage for the device base, and a connector configured to connect the circuit assembly to the device base, where the device base is configured to connect to a device mounting substrate on a substrate side of the device base, and where the circuit assembly is configured to be at least partially located on an opposing side of the device base, the opposing side opposing the substrate side.

Abstract: Time transfer systems and methods in Flexible Ethernet (FlexE) between a first node and a second node include detecting a timestamp point of reference in FlexE overhead and sampling a time based thereon; communicating samples of the timestamp point of reference between the first node and the second node; and determining a time delay between the first node and the second node based on the samples.