Abstract: Example embodiments relate to methods for continuous photovoltaic cell stringing and photovoltaic cell assemblies. An example method includes providing a foil in a provision direction in a continuous manner. The method also includes cutting at least one slit into the foil along the provision direction. Additionally, the method includes creating at least one slit opening by folding open the foil at a location of the at least one slit. Further, the method includes providing at least one electrically conductive wire near a first surface of the foil along the provision direction aligned with the at least one slit opening in a continuous manner. Yet further, the method includes folding back the foil at the at least one slit opening after the electrically conductive wire provision such that the at least one electrically conductive wire changes its position.

Abstract: The present disclosure related to a method for interconnecting photovoltaic cells in order to form a photovoltaic cells assembly is provided. The method comprises the steps of providing a first photovoltaic cell comprising a first surface, a second surface, a first edge, and a second edge, arranging a conductive wire on the first surface of the first photovoltaic cell according to a certain pattern, and attaching the conductive wire to the first surface of the first photovoltaic cell with the aid of a first non-conductive yarn by stitching in the area of the first edge of the first photovoltaic cell according to a first stitch type.

Abstract: Example embodiments relate to partially translucent photovoltaic modules and methods for manufacturing partially translucent photovoltaic modules. One embodiment includes a method for electrically interconnecting a plurality of thin-film photovoltaic plates. The method includes positioning a plurality of thin-film photovoltaic plates side by side. The thin-film photovoltaic plates are partially translucent or non-translucent. The method also includes providing at least one connection element on a surface of each of the plurality of thin-film photovoltaic plates. The at least one connection element includes a plurality of electrically conductive wires arranged in a grid structure. Further, the method includes physically separating each connection element into a first connection part that includes a plurality of first electrically interconnected, conductive wires and a second connection part that includes a plurality of second electrically interconnected, conductive wires.

Abstract: Example embodiments relate to partially translucent photovoltaic modules and methods for manufacturing partially translucent photovoltaic modules. One embodiment includes a method for electrically interconnecting a plurality of thin-film photovoltaic plates. The method includes positioning a plurality of thin-film photovoltaic plates side by side. The thin-film photovoltaic plates are partially translucent or non-translucent. The method also includes providing at least one connection element on a surface of each of the plurality of thin-film photovoltaic plates. The at least one connection element includes a plurality of electrically conductive wires arranged in a grid structure. Further, the method includes physically separating each connection element into a first connection part that includes a plurality of first electrically interconnected, conductive wires and a second connection part that includes a plurality of second electrically interconnected, conductive wires.

Abstract: The disclosed technology generally relates to chalcogenide thin films, and more particularly to ternary and quaternary chalcogenide thin films having a wide band-gap, and further relates to photovoltaic cells containing such thin films, e.g., as an absorber layer. In one aspect, a method of forming a ternary or quaternary thin film chalcogenide layer containing Cu and Si comprises depositing a copper layer on a substrate. The method additionally comprises depositing a silicon layer on the copper layer with a [Cu]/[Si] atomic ratio of at least 0.7, and thereafter annealing in an inert atmosphere. The method further includes performing a first selenization or a first sulfurization, thereby forming a ternary thin film chalcogenide layer on the substrate. In another aspect, a composite structure includes a substrate having a service temperature not exceeding 600° C.

Abstract: The disclosed technology generally relates to chalcogenide thin films, and more particularly to ternary and quaternary chalcogenide thin films having a wide band-gap, and further relates to photovoltaic cells containing such thin films, e.g., as an absorber layer. In one aspect, a method of forming a ternary or quaternary thin film chalcogenide layer containing Cu and Si comprises depositing a copper layer on a substrate. The method additionally comprises depositing a silicon layer on the copper layer with a [Cu]/[Si] atomic ratio of at least 0.7, and thereafter annealing in an inert atmosphere. The method further includes performing a first selenization or a first sulfurization, thereby forming a ternary thin film chalcogenide layer on the substrate. In another aspect, a composite structure includes a substrate having a service temperature not exceeding 600° C.

Abstract: The disclosed technology generally relates to chalcogenide thin films, and more particularly to ternary and quaternary chalcogenide thin films having a wide band-gap, and further relates to photovoltaic cells containing such thin films, e.g., as an absorber layer. In one aspect, a method of forming a ternary or quaternary thin film chalcogenide layer containing Cu and Si comprises depositing a copper layer on a substrate. The method additionally comprises depositing a silicon layer on the copper layer with a [Cu]/[Si] atomic ratio of at least 0.7, and thereafter annealing in an inert atmosphere. The method further includes performing a first selenization or a first sulfurization, thereby forming a ternary thin film chalcogenide layer on the substrate. In another aspect, a composite structure includes a substrate having a service temperature not exceeding 600° C.

Abstract: A method for chemically cleaning and passivating a chalcogenide layer is provided, wherein the method comprises bringing the chalcogenide layer into contact with an ammonium sulfide containing ambient, such as an ammonium sulfide liquid solution or an ammonium sulfide containing vapor. Further, a method for fabricating photovoltaic cells with a chalcogenide absorber layer is provided, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; bringing the chalcogenide semiconductor layer into contact with an ammonium sulfide containing ambient, thereby removing impurities and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer.

Abstract: A method for chemically cleaning and passivating a chalcogenide layer is provided, wherein the method comprises bringing the chalcogenide layer into contact with an ammonium sulfide containing ambient, such as an ammonium sulfide liquid solution or an ammonium sulfide containing vapor. Further, a method for fabricating photovoltaic cells with a chalcogenide absorber layer is provided, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; bringing the chalcogenide semiconductor layer into contact with an ammonium sulfide containing ambient, thereby removing impurities and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer.

Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract: The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 ?m×2 ?m) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract: The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 ?m×2 ?m) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device.

Abstract: A semiconductor device is disclosed. In one aspect, the device comprises a channel area, the channel area comprising a channel layer in which charge carriers can move when the transistor is turned on, in order to pass a current through the transistor. The device further comprises a source area and a drain area contacting the channel layer for providing current to and from the channel layer. The method further comprises a gate electrode, preferably provided with a gate dielectric between the gate electrode and the channel layer. The channel layer may comprise a III-V material, and the source and drain areas comprise SiGe, being SixGe1-x, with x between 0 and 100%, arranged so that heterojunctions are present between III-V material and SiGe, wherein the heterojunctions are oriented so as to intersect with the gate dielectric or the gate electrode.