Abstract: A write compression buffer is connected to a CPU bus and to a memory controller to provide write cycle compression in which plural partial write requests to the same memory address are compressed into a single memory write cycle. The buffer has a plurality of buffering level.

Abstract: A system and method for connecting a short word length memory to a significantly wider bus operated in an address/data multiplexing mode. A mode of operation is defined for the bus whereby the bus lines are divided for purposes of memory accessing into a data group and an address group. The data group is operable bidirectionally to read or write memory, using the addresses provided on the group of address lines. This architecture and practice is particularly suited for a boot ROM used with processors, in that such ROMs are normally of relatively short word length while the processors are of relatively long word length and are accordingly connected to buses of similar long word length. Bridge logic interfaces the processor bus to the ROM for sequencing, timing and supplemental control in converting the data from the ROM format to the processor format.

Abstract: A method and system for managing the utilization of power is provided. In a system having one or more devices, such as a memory subsystem having one or more banks of memory, the amount of power necessary for the operation of one or more of the devices is monitored and if possible, the power being supplied to one or more of the devices is reduced. A scoreboard located within a memory controller is used to retain the available power modes for each of the devices. When it is determined that it is desirable to reduce the power being supplied to a particular device, then the scoreboard is accessed in order to determine the lowest power level available for the device. Using this information, an amount of power commensurate with the lowest power level is applied to the device, thereby reducing the amount of power being applied to the device. In one aspect of the invention, a device is automatically placed in its lowest power level when it has not been accessed for a preselected amount of time.