Abstract: The present disclosure relates to methods and systems to manage traffic density in a transportation system, and by doing so, maintain, in one embodiment, traffic flows near optimum levels to maximize road capacity and minimize travel times. The method includes, in one embodiment, a mechanism for vehicles to request road access from a centralized control, a queuing system that allows road access to be granted to individual vehicles over an extended period of time in a fair and organized fashion, a measurement system that allows traffic flow and density throughout the system to be determined in real-time, and an enforcement and fraud prevention mechanism to ensure that the rules and permissions imposed by the system are followed.

Abstract: The present disclosure relates to methods and systems to manage traffic density in a transportation system, and by doing so, maintain, in one embodiment, traffic flows near optimum levels to maximize road capacity and minimize travel times. The method includes, in one embodiment, a mechanism for vehicles to request road access from a centralized control, a queuing system that allows road access to be granted to individual vehicles over an extended period of time in a fair and organized fashion, a measurement system that allows traffic flow and density throughout the system to be determined in real-time, and an enforcement and fraud prevention mechanism to ensure that the rules and permissions imposed by the system are followed.

Abstract: The present disclosure relates to methods and systems to manage traffic density in a transportation system, and by doing so, maintain, in one embodiment, traffic flows near optimum levels to maximize road capacity and minimize travel times. The method includes, in one embodiment, a mechanism for vehicles to request road access from a centralized control, a queuing system that allows road access to be granted to individual vehicles over an extended period of time in a fair and organized fashion, a measurement system that allows traffic flow and density throughout the system to be determined in real-time, and an enforcement and fraud prevention mechanism to ensure that the rules and permissions imposed by the system are followed.

Abstract: The present disclosure relates to methods and systems to manage traffic density in a transportation system, and by doing so, maintain, in one embodiment, traffic flows near optimum levels to maximize road capacity and minimize travel times. The method includes, in one embodiment, a mechanism for vehicles to request road access from a centalized control, a queuing system that allows road access to be granted to individual vehicles over an extended period of time in a fair and organized fashion, a measurement system that allows traffic flow and density throughout the system to be determined in real-time, and an enforcement and fraud prevention mechanism to ensure that the rules and permissions imposed by the system are followed.

Abstract: A circuit for translating pixel data to be displayed on the output display of a computer system including a plurality of color index maps for providing a first set of digital values of shades to produce a final color on an output display in response to color index values; and a plurality of gamma correction maps for providing a second set of digital values of shades to produce a final color on an output display in response to the first set of digital values of shades.

Abstract: In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.

Abstract: In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.

Abstract: A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the memory cycle time of each to of the RAMs.

Abstract: A method and apparatus for clearing a Z-buffer in a raster scanned, computer controlled video display system having a frame buffer and a Z-buffer is disclosed. The method includes the step of writing a plurality of bits into pixel locations of the frame buffer, which pixel locations will be cleared in the Z-buffer and on the screen of the video display. Those plurality of bits invalidating the Z values in the Z-buffer corresponding to those pixel locations.

Abstract: A graphics processor is coupled to a plurality of RAMs (Random Access Memories) for storing a frame of a display. The processor provides a separate RAS (Row Address Strobe) signal and a separate CAS (Column Address Strobe) signal to each of the memories so that row and/or column addresses to each of the RAMs can be latched using a staggered timing sequence. Data can be written into or read from memory using this staggering technique, wherein overall data transfer rate is faster than the memory cycle time of each of the RAMs.

Abstract: A method for updating a single ported, pipelined Z-buffer where the Z-buffer is updated only after determining the beginning and ending location of a continuous group of pixel locations requiring updating in the Z-buffer.

Abstract: An improvement for providing color information in a raster scanned video display apparatus where color data is stored in a frame buffer for each pixel in addition to color data. The color data is coupled to a crossbar switch to provide several sets of color data at the output of the switch. A multiplexer receives these several sets of color information and selects between them based on the color mode data. This permits the same color code to represent more than a single color. In a display, color in windows may then be generated from different programs, eliminating color-code dependencies between programs.

Abstract: YA dual clock shift register for use in a computer display system for converting a higher resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus. The dual clock shift register includes a first shift register which is used to apportion a second shift register between control by two different clock rates.