Abstract: An automatic test apparatus for testing the digital functionality of multiple semiconductor integrated circuit devices simultaneously connected to the apparatus generates data patterns suitable for testing at least one of the devices. Stimulus test signals of the data patterns are replicated and distributed to the devices. Expected response signals of the devices for the test signals are also replicated and distributed to comparators for comparing the actual response of the devices with the expected response.

Abstract: An automated test and evaluation sampling system includes a fast pattern memory (130) and a slow pattern memory (137) storing first and second sets of tests states, respectively. Stimulus logic (131) is connected to the fast pattern memory to read the first set of test states at a first rate and stimulate a device under test (133) according to the first set of test states. Compare logic (135) is connected to the slow pattern memory to read the second set of test states at a second rate which is slower on average than the first rate and to compare the second set of test states with a sampled output signal from the device under test.

Abstract: A calibration method and system for substantially reducing one of the components of timing error in automatic test systems. The timing associated with digital stimulus and response circuitry in a tester is different for positive and negative signal transitions. This inherent timing difference is normally measured and compensated for during the tester calibration process. The present method and system uses a short circuited transmission line as a pulse generator to achieve superior stability and accuracy when calibrating transition dependent timing in automatic test systems.

Abstract: A function array system includes a controller, a test function and specific memories to accelerate the execution of a VLSI device test program by preloading register files associate with each hardware function in the tester with test set-up information. Test information is transferred to the register files only once when the test program is initially downloaded into the tester. A simple controller sequences a test set-up pointer during test execution.

Abstract: A pattern sequence control system utilizing a control RAM to provide pattern control information only when a change in pattern sequence control is required, thereby significantly reducing the amount of pattern control memory required. The pattern sequence control system utilizes a single pattern address counter for sequential patterns and a single loop address counter for looping pattern. The pattern address counter and loop address counter provide the pattern memory address for all pattern memory regardless of the number of tester channels. A cycle counter determines the number of test cycles that a sequential pattern or repeating pattern will be applied. A loop length counter and loop counter are used to control pattern looping.

Abstract: A timing system using shared address generator(s) to address memories that form the basis of each pin's timing reference generator can reduce the amount of hardware required to implement a "Timing Generator Per Pin" architecture in a VLSI tester by at least 50%.

Abstract: A reconfigurable resource architecture enhances a test system's utilization by allowing product-mix dependent allocation of test system resources. The test system resources can be configured to test several device types with different pin counts simultaneously. The configuration can be changed to accommodate various product mixes based on pin count.

Abstract: Simple polynomial function generators are used to generate pseudo random test patterns and perform signature analysis on a per pin basis in the control logic in LSI/VLSI test systems.

Abstract: Disclosed is a test system and a method for providing a timing function that dynamically calculates and adjusts the phase delay between an internal timing reference and an externally derived signal. This is accomplished by providing a timing generator for providing a master timing reference signal, first, second and third counters preset at the beginning of each test cycle to each provide a count responsive to the timing reference signal, first and second multiplexers, each associated with one of the first and second counters, and first and second comparators for comparing the contents of each of the first and second multiplexers with the count of an associated counter and producing a timing edge when a count match occurs.