Abstract: An architecture is provided for testing and emulating an integrated circuit with embedded function blocks. The output nodes of the function blocks are connected through a tri-state buffer to a test bus which in turn is connected to configurable external pins. The external pins multiplex the normal I/O in normal mode and the test bus I/O in the test mode. The test bus is also connected through multiplexers to input nodes of function blocks. In test mode, the function block nodes are accessed through the test bus. For emulation of an embedded microcontroller or microprocessor, the internal connections of the microcontroller (or microprocessor) are brought out to those external pins which in normal operation are connected only to the microcontroller and not to any other function block. An in-circuit emulator (ICE) emulating the microcontroller is connected to the other function blocks through those external pins.