Abstract: A glitch-free clock switch circuit for an integrated circuit having a plurality of asynchronous clocks, wherein only one clock is selected at a time, and wherein the clock switching circuitry for switching from a currently selected clock to an inactive clock to next be selected is activated only for the time it takes to complete the switching. The clock switch circuit includes at least three sets of clock drivers, wherein each set is comprised of two drivers and separate clock drivers are each associated with the output clock, the currently selected clock and the clock to next be selected, respectively. An edge detector turns on these clock drivers in response to a clock select signal, and a set of synchronizers receive and synchronize the clock select signal first with the output clock and then with the currently selected clock and the clock to next be selected, respectively.

Abstract: There is disclosed a loop counter reload circuit loads an initial count value into a counter and a shadow register. A count value output from the counter is changed by a predetermined displacement resulting in a changed count value. The count value from the shadow register is loaded into the counter if the changed count value has reached a predetermined reference value, and otherwise the changed count value is loaded into the counter.

Abstract: In accordance with the present invention, a method and apparatus are provided for controlling an N-bit barrel shifter to shift the bits of an input word by a shift value. The method includes the steps of performing a ones' complement of an m-bit binary representation of a shift value to generate an input when the shift direction takes on a first direction and passing the binary representation of the shift value as the input when the shift direction takes on a second direction. Decoding the input into 2.sup.m control signals and generating a plurality of groups of control signals from the 2.sup.m control signals. Selecting one of the plurality of groups of control signals as the control activation for the barrel shifter. The apparatus provides bits of a binary representation of the shift value are passed through a plurality of exclusive OR gates and provided as inputs to a first decoder. The first decoder decodes the inputs into a plurality of bits used as control signals.

Abstract: There is an equalizer or a receiver including an equalizer which has means to factor detected symbols transmitted over a transmission channel into a magnitude portion and a repetitive phase portion. The receiver further has means to generate modified tap weights by multiplying the repetitive phase portion by tap weights representative of the channel. Modified tap weights are generated by multiplying the repetitive phase portion by tap weights representative of the channel. The modified tap weights are convolved with bits of possible states to generate possible transmitted symbols. A maximum likelihood sequence estimation is performed on the possible transmitted symbols comparing each possible transmitted symbol to a received symbol to generate an MLSE detected symbol. The detected symbol is multiplied by a rotating vector to generate a decoded symbol.