Abstract: A signal detector device and method includes a quadrature demodulator configured to receive an input signal, a first reference signal, and a second reference signal in quadrature with the first reference signal, the quadrature demodulator further configured to produce a plurality of output signals from the input signal and the first and the second reference signal, the plurality of output signals indicating the amplitude and phase of the input signal, and one or more inverting circuits, the inverting circuits having a first and a second programmable output polarity, the plurality of output signals being output by the quadrature demodulator when the inverting circuits are set to the first programmable output polarity, the plurality of output signals being inverted and output by the quadrature demodulator when the inverting circuits are set to the second programmable output polarity

Abstract: In accordance with an embodiment a beamforming circuit having a radio frequency (RF) front end and a plurality of beamforming delay circuits coupled to the RF front end. Each of the plurality of beamforming delay circuits includes a common delay circuit and a plurality of individual delay circuits coupled to the common delay circuit. Each of the individual delay circuits are configured to be coupled to an antenna element of a beamforming array.

Abstract: In accordance with an embodiment a beamforming circuit having a radio frequency (RF) front end and a plurality of beamforming delay circuits coupled to the RF front end. Each of the plurality of beamforming delay circuits includes a common delay circuit and a plurality of individual delay circuits coupled to the common delay circuit. Each of the individual delay circuits are configured to be coupled to an antenna element of a beamforming array.

Abstract: In accordance with an embodiment a beamforming circuit having a radio frequency (RF) front end and a plurality of beamforming delay circuits coupled to the RF front end. Each of the plurality of beamforming delay circuits includes a common delay circuit and a plurality of individual delay circuits coupled to the common delay circuit. Each of the individual delay circuits are configured to be coupled to an antenna element of a beamforming array.

Abstract: One embodiment described is an apparatus that includes an active device structured in a semiconductor body. The semiconductor body may include a gate terminal to receive a switched bias signal, and a bulk terminal to receive a forward body-bias signal. A first circuit portion may be coupled to the gate terminal to provide the switched bias signal, and a second circuit portion may be coupled to the bulk terminal to provide the forward body-bias signal.

Abstract: A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.

Abstract: In accordance with an embodiment, an oscillator includes a tank circuit and an oscillator core circuit having a plurality of cross-coupled compound transistors coupled to the tank circuit. Each of the plurality of compound transistors includes a bipolar transistor and a field effect transistor (FET) having a source coupled to a base of the bipolar transistor.

Abstract: In accordance with an embodiment, an oscillator includes a tank circuit and an oscillator core circuit having a plurality of cross-coupled compound transistors coupled to the tank circuit. Each of the plurality of compound transistors includes a bipolar transistor and a field effect transistor (FET) having a source coupled to a base of the bipolar transistor.

Abstract: A disclosed circuit arrangement may include a power detector. A multiplexer circuit may be coupled to the power detector. The multiplexer circuit may include at least two switching sections, one of the switching sections to pass a radio frequency (RF) signal generated based on a first modulation scheme to the power detector and another of the switching sections to pass an RF signal generated based on a second modulation scheme to the power detector.

Abstract: The present disclosure relates to techniques for simulating electrical inductance.

Abstract: The present disclosure relates to constructing and operating a transistor or other active device with significantly reduced flicker noise.

Abstract: The present disclosure relates to constructing and operating a transistor or other active device with significantly reduced flicker noise.

Abstract: One aspect is an integrated circuit arrangement. The arrangement includes a first terminal, which can be brought to a first supply potential, a second terminal, which can be brought to a second supply potential, and a supply potential path formed between the first terminal and the second terminal. There is an electrostatic discharge element at least in the supply potential path. There is a signal input pad, to which an input signal can be applied and a signal output, at an output signal can be provided. A first inductance is arranged between the signal input pad and the signal output, and a second inductance is arranged between the signal output and the first terminal.

Abstract: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: The present disclosure relates to constructing and operating a transistor or other active device with significantly reduced flicker noise.

Abstract: The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices.

Abstract: The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices.

Abstract: Semiconductor device having an amplifier. In one embodiment, the amplifier includes a first amplifier path including a first input and a second amplifier path including a second input. An inductance having a connectable node is connected between the first and second inputs, the connectable node being symmetrically connected between the first and second inputs. At least one ESD protection structure is connected to the connectable node. In one embodiment, the semiconductor device is used in a communications device.

Abstract: The present disclosure relates to constructing and operating a transistor or other active device with significantly reduced flicker noise.