Abstract: A sensor (400) for sensing jitter in a clock signal has a DLL (402, 310, 312) for locking a clock signal and a delayed version of the clock signal. The sensor comprises a delay line (402) having a first number of cascaded controllable delay segments. The DLL uses a second number of the cascaded delay segments for generating a delay of an average clock period of the clock signal. The second number is smaller than the first number. The sensor also has a comparator (408) for supplying a sensor output signal representative of a comparison of the clock signal and a further delayed version of the clock signal. The further delayed version of the clock signal is obtained from an output of a specific one of the delay segments located in the delay line after the second number of cascaded delay segments.

Abstract: A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.

Abstract: A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.

Abstract: A sensor (400) for sensing jitter in a clock signal has a DLL (402, 310, 312) for locking a clock signal and a delayed version of the clock signal. The sensor comprises a delay line (402) having a first number of cascaded controllable delay segments. The DLL uses a second number of the cascaded delay segments for generating a delay of an average clock period of the clock signal. The second number is smaller than the first number. The sensor also has a comparator (408) for supplying a sensor output signal representative of a comparison of the clock signal and a further delayed version of the clock signal. The further delayed version of the clock signal is obtained from an output of a specific one of the delay segments located in the delay line after the second number of cascaded delay segments.

Abstract: A digital-to-analog converter having a ladder resistor portion for generating a plurality of quantization signals of predetermined values based on reference signals of predetermined values and a quantization switch portion for selectively outputting one of the quantization signals in accordance with a digital input value. The ladder resistor portion is coupled to at least one resistor for generating a signal of a value which corresponds to a desired signal level of a signal to be added. A switch provided for supplying the signal of the value corresponding to the desired signal level to an output of the switch portion in response to a timing signal synchronized with the signal to be added.