Abstract: Apparatus and method for IR-drop and supply noise measurements in electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.

Abstract: The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (?A, ?B, ?C) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.

Abstract: The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (?A, ?B, ?C) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.

Abstract: Apparatus and method for IR-drop and supply noise measurements electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.

Abstract: The present invention relates to a detection circuitry for detecting bonding conditions on segmented bond pads of a semiconductor device, the bonding conditions representing good or bad contacts on the bond pads. The detection circuitry comprises a segmented bond pad (1, 11) having at least two parts (2, 3, 12, 13) being electrically separated from each other, and a supplying unit (S1, S2, R1, R2) being adapted for supplying predetermined signals to at least one of the at least two parts of the segmented bond pad. Furthermore, a detector (4, 14) is provided for receiving from at least one of the at least two parts of the segmented bond pad sensing signals derived from said predetermined signals, and for determining the bonding conditions based on said received sensing signals indicative of a good or bad bonding contact on the segmented bond pad.

Abstract: An integrated circuit comprises a plurality of sensing circuits (12), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register (11) for shifting digital data signals that represent the respective reference values from a successive approximation update circuit (14) to the sensing circuits (12) and back to the successive approximation update circuit (14). Detection results of the sensing circuits (12) are shifted to the successive approximation update circuit (14) with the digital data signals. The successive approximation update circuit (14) is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit (14) is shared by a plurality of sensing circuits (12).

Abstract: The invention relates to a semiconductor device comprising a test structure (100) for detecting variations in the structure of the semiconductor device, the test structure (100) comprising a first supply rail (110), a second supply rail (120), a ring oscillator (130) coupled between the first supply rail (110) and second supply rail (120), the ring oscillator (130) having an output (132) for providing a test result signal, and an array (140) of individually controllable transistors (142) coupled in parallel between the first supply rail (110) and the ring oscillator (130). Variations in the current output of the respective transistors (142) in the array (140) lead to variations in the respective output frequencies of the ring oscillator (130). This gives a qualitative indication of the aforementioned structural variations.

Abstract: The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50).

Abstract: An integrated circuit (1) comprises a monitor (M1, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (M1, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SR1, SR2, SR3) and is operable to output monitor data through the shift register (SR1, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.

Abstract: A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.

Abstract: An integrated circuit is provided with a distributed supply voltage monitoring system in which a single controller controls a plurality of voltage monitors located in respective modules of the integrated circuit. The controller and each circuit form a successive approximation analogue to digital converter Such a system enables a small size monitoring circuit to be realized for every module of the integrated circuit.

Abstract: A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.

Abstract: An integrated circuit is provided with a distributed supply voltage monitoring system in which a single controller controls a plurality of voltage monitors located in respective modules of the integrated circuit. The controller and each circuit form a successive approximation analogue to digital converter Such a system enables a small size monitoring circuit to be realized for every module of the integrated circuit.

Abstract: The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50).

Abstract: In an AD converter a primary ?A-modulator digitizes the analog input signal. The quantization noise generated thereby is isolated in the analog domain and digitized in a secondary ?A-modulator. The quantization noise so digitized by the secondary ?A-modulator is subtracted from the quantization noise in the output of the primary ?A-modulator. Because the quantization noise generated by the primary ?A-modulator is subject to filtering (shaping) the quantization noise digitized in the secondary ?A-modulator should also be filtered. This is performed by similar filtering in the feedback path of the secondary ?A-modulator.

Abstract: An integrated circuit comprises a plurality of sensing circuits (12), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register (11) for shifting digital data signals that represent the respective reference values from a successive approximation update circuit (14) to the sensing circuits (12) and back to the successive approximation update circuit (14). Detection results of the sensing circuits (12) are shifted to the successive approximation update circuit (14) with the digital data signals. The successive approximation update circuit (14) is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit (14) is shared by a plurality of sensing circuits (12).

Abstract: For a comb filter arrangement, for example, for separating a color picture signal into a modulated chrominance subcarrier and a luminance signal, while generating two comb filter function, a one-stage median filter (21) is provided in which the amplitudes of the simultaneously available signals of three picture lines and the two comb filter functions are compared with each other in a comparator stage which supplies logical comparison signals to a selection logic (30) in dependence upon the comparison results. The selection logic (30) constantly determines the signal having the middle instantaneous amplitude of the signals applied to the comparator stage on the basis of the comparison signals, and applies this signal to the medium filter output.