Abstract: A system is for transmitting data in a network and includes emitter nodes, each including a transmitter for transmitting requests for data transmission. The system may also include a receiver node receiving the data transmission from the emitter nodes and including a first memory for storing data transmitted by each emitter node, a second memory for storing the requests, and a transmitter. The data may be transmitted from the emitter nodes to the receiver node when memory space is available in the first memory to receive data. The transmitter of the receiver node may transmit to each emitter node an acknowledgement message when memory space is available in the first memory to receive at least a portion of the data transmitted. Each emitter node may establish a communication link with the receiver node and transmits the data based upon the acknowledgement message. The communication link may be locked until all data is transmitted.

Abstract: A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.

Abstract: A bandwidth allocator to allocate in real time shared resources of a network on-chip is disclosed. The bandwidth allocator routes data packets between elements of the network in response to requests to access the shared resources. The bandwidth allocator could include a plurality of network interfaces to process the data packets to be routed within the network and a plurality of routers for routing the data packets through the network. A processor, distributed within the routers, controls the routers and the transmission of each data of the data packets through the routers to provide a bandwidth for each data flow. The network interfaces is adapted to fill a header field of each data packet with header field information depending on a requested bandwidth. The processor controls the transmission of the data packets through the routers as a function of the value of the header field information of each data packet.

Abstract: A system for routing a data packet between N elements includes N network interfaces respectively connected to the N elements, with N being an even integer, and an on-chip packet-switched communication network arranged in a ring structure. The packet-switched communication network includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each pair of ring links couples two adjacent routers in the ring structure, and each ring link provides two virtual channels. There are N/2 pairs of opposite uni-directional crossing links, with each pair of crossing links coupling two diametrically opposite routers in the ring structure.

Abstract: This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: retrieving from the first device request packets comprising request control data for controlling data transfer and actual request data to be transferred; storing said request control and data to be transferred in memory means provided in an network interface (NI); and elaborating data packets to be transferred to the second device through said network, said data packets comprising a header and a payload elaborated from said control data and said actual data, respectively; The control data and the actual data to be transferred are stored in separate first and second memory means.

Abstract: Systems and methods for transferring a stream of at least one data packet between a first electronic device and second electronic device through a network-on-chip are disclosed. These systems and methods can comprise storing data packets in memory means provided in a network interface and transferring data packets from the memory means to the second electronic device. Packets can be transferred from the memory means after a quantity of packets is stored in the memory means, the quantity of packets being determined according to a value of a control parameter.

Abstract: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Abstract: A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.

Abstract: A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.

Abstract: A system is for transmitting data in a network and includes emitter nodes, each including a transmitter for transmitting requests for data transmission. The system may also include a receiver node receiving the data transmission from the emitter nodes and including a first memory for storing data transmitted by each emitter node, a second memory for storing the requests, and a transmitter. The data may be transmitted from the emitter nodes to the receiver node when memory space is available in the first memory to receive data. The transmitter of the receiver node may transmit to each emitter node an acknowledgement message when memory space is available in the first memory to receive at least a portion of the data transmitted. Each emitter node may establish a communication link with the receiver node and transmits the data based upon the acknowledgement message. The communication link may be locked until all data is transmitted.

Abstract: A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.

Abstract: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Abstract: A bandwidth allocator to allocate in real time shared resources of a network on-chip is disclosed. The bandwidth allocator routes data packets between elements of the network in response to requests to access the shared resources. The bandwidth allocator could include a plurality of network interfaces to process the data packets to be routed within the network and a plurality of routers for routing the data packets through the network. A processor, distributed within the routers, controls the routers and the transmission of each data of the data packets through the routers to provide a bandwidth for each data flow. The network interfaces is adapted to fill a header field of each data packet with header field information depending on a requested bandwidth. The processor controls the transmission of the data packets through the routers as a function of the value of the header field information of each data packet.

Abstract: A system for routing a data packet between N elements includes N network interfaces respectively connected to the N elements, with N being an even integer, and an on-chip packet-switched communication network arranged in a ring structure. The packet-switched communication network includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each pair of ring links couples two adjacent routers in the ring structure, and each ring link provides two virtual channels. There are N/2 pairs of opposite uni-directional crossing links, with each pair of crossing links coupling two diametrically opposite routers in the ring structure.

Abstract: A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue.

Abstract: An ATM routing switch has a buffer circuit for holding cells located on queues at output ports, the buffer having a first reserve buffer capacity for cells of a first type requiring integrity of cell transmission and a first designation for use in determining a permitted path through the network, a second reserve buffer capacity for cells of the first type having a second designation for use in determining a different permitted path in the network and a third reserve buffer capacity for cells of a second type accepting some loss of cells in transmission, flow control circuitry operating to limit input of cells of either the first or second type if predetermined thresholds for the first, second or third buffer capacities are reached.

Abstract: An ATM routing switch has a plurality of output ports for handling digital signal cells on a first type requiring integrity of cell transmission and a second type accepting some loss of cells in transmission, the output ports having control circuitry to provide a plurality of queues of cells at each output port, each queue comprising only cells of a single type while each port outputs a mixture of cells of both types on a common output path flow control indicators on incoming cells being used to inhibit output of cells along any path to a destination for which a flow control indicator has indicated congestion.

Abstract: An ATM routing switch for bidirectional transmission of at least two types of cell, one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity for cells of the first type, a second reserve buffer capacity for cells of said second type and control circuitry for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity has been reached by input of cells of said second type.

Abstract: An ATM routing switch has a plurality of input and output ports and a buffer for holding a plurality of ATM cells, the cells being held in the buffer as a plurality of queues (F0-F7), each formed as a chained list of addresses with front and back pointers identifying ends of each queue.

Abstract: A network of ATM routing switches transmits digital signal cells of a first type requiring integrity of transmission and a second type accepting some loss in transmission, each switch has buffer circuitry. a plurality of output ports each having a plurality of queues of cells awaiting output, each output port having control circuitry to provide in an output frame control bits indicating the type of cell, a path identifier and the existence of flow congestion at the routing switch which it outputting the frame, thereby inhibiting transmission of further frames to that location until a frame is received from that location indicating that the congestion is cleared.