Patents by Inventor Marcelo Yuffe
Marcelo Yuffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9870301Abstract: A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.Type: GrantFiled: March 31, 2014Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: Tsvika Kurts, Eilon Hazan, Sean T. Baartmans, Marcus R. Winston, Rony Ghattas, Arie Bernstein, Todd M. Witter, Marcelo Yuffe
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Publication number: 20150278058Abstract: A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Inventors: TSVIKA KURTS, EILON HAZAN, SEAN T. BAARTMANS, MARCUS R. WINSTON, RONY GHATTAS, ARIE BERNSTEIN, TODD M. WITTER, MARCELO YUFFE
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Patent number: 7504856Abstract: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.Type: GrantFiled: May 7, 2007Date of Patent: March 17, 2009Assignee: Intel CorporationInventors: Tsvika Kurts, Alex Waizman, Marcelo Yuffe, Ziv Shmuely
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Publication number: 20070285123Abstract: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.Type: ApplicationFiled: May 7, 2007Publication date: December 13, 2007Applicant: INTEL CORPORATIONInventors: Tsvika Kurts, Alex Waizman, Marcelo Yuffe, Ziv Shmuely
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Patent number: 7230450Abstract: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.Type: GrantFiled: May 18, 2004Date of Patent: June 12, 2007Assignee: Intel CorporationInventors: Tsvika Kurts, Alex Waizman, Marcelo Yuffe, Ziv Shmuely
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Patent number: 7216240Abstract: A bus agent is described having a controller to cause assertion of a power signal if an address is to be transferred to a receiving bus agent, the power signal to enable a set of input address sense amplifiers of the receiving agent, prior to the receiving bus agent receiving the address.Type: GrantFiled: December 11, 2002Date of Patent: May 8, 2007Assignee: Intel CorporationInventors: Tsvika Kurts, Doron Orenstien, Marcelo Yuffe
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Patent number: 7152167Abstract: An approach for data bus power control. Data input sense amplifiers of a request agent are enabled prior to a data phase of a transaction according to a data bus power control signal. Once enabled, the data input sense amplifiers can capture data provided during the data phase of the read transaction. Accordingly, the data input sense amplifiers of the request agent are disabled according to the power control signal once the data phase of the read transaction is complete.Type: GrantFiled: December 11, 2002Date of Patent: December 19, 2006Assignee: Intel CorporationInventors: Tsvika Kurts, Doron Orenstien, Marcelo Yuffe
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Patent number: 7114038Abstract: For one embodiment, a computer system includes both high power and low power buses coupling a processor to a controller. When the processor is in a high power mode, its cache is snooped by the controller via the high power bus. When the processor is in a low power mode, its cache is snooped by the controller via the low power bus.Type: GrantFiled: December 28, 2001Date of Patent: September 26, 2006Assignee: Intel CorporationInventors: Doron Orenstien, Marcelo Yuffe
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Patent number: 6970010Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.Type: GrantFiled: August 18, 2003Date of Patent: November 29, 2005Assignee: Intel CorporationInventors: Jeffrey R. Wilcox, Noam Yosef, Marcelo Yuffe
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Publication number: 20050258861Abstract: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.Type: ApplicationFiled: May 18, 2004Publication date: November 24, 2005Inventors: Tsvika Kurts, Alex Waizman, Marcelo Yuffe, Ziv Shmuely
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Publication number: 20040128416Abstract: Various devices and methods are described. According to a first method performed by a processor having data sense amplifiers that receive data from a data bus portion of a front side bus: data sense amplifiers are enabled in response to an address strobe being asserted. The data sense amplifiers are then disabled at least in response to a queue being empty. The queue keeps track of transactions yet to be performed over the front side bus. According to a second method performed by a processor having data sense amplifiers that receive data from a data bus portion of a front side bus and address sense amplifiers that receive an address from an address bus portion of the front side bus: address sense amplifiers are enabled in response to a request indication being asserted. The data sense amplifiers are enabled in response to an address strobe being asserted. The address sense amplifiers are disabled in response to the request indication being de-asserted.Type: ApplicationFiled: May 12, 2003Publication date: July 1, 2004Inventors: Tsvika Kurts, Doron Orenstien, Marcelo Yuffe
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Publication number: 20040117670Abstract: An approach for data bus power control. Data input sense amplifiers of a request agent are enabled prior to a data phase of a transaction according to a data bus power control signal. Once enabled, the data input sense amplifiers can capture data provided during the data phase of the read transaction. Accordingly, the data input sense amplifiers of the request agent are disabled according to the power control signal once the data phase of the read transaction is complete.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Inventors: Tsvika Kurts, Doron Orenstien, Marcelo Yuffe
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Publication number: 20040117671Abstract: A bus agent is described having a controller to cause assertion of a power signal if an address is to be transferred to a receiving bus agent, the power signal to enable a set of input address sense amplifiers of the receiving agent, prior to the receiving bus agent receiving the address.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Inventors: Tsvika Kurts, Doron Orenstien, Marcelo Yuffe
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Patent number: 6747475Abstract: A circuit for driving and receiving signals on a bus line includes a pull-up switch and a pull-down switch. The pull-up switch has an impedance that matches the characteristic impedance of the bus line. The pull-down switch has an impedance of about half of the characteristic impedance of the bus line. When the circuit is receiving a signal or driving a logic high signal on the bus line, the pull-up switch is enabled so that the bus line voltage is pulled up, while the pull-down switch is disabled to prevent the pull-down switch from pulling down the bus line voltage. When the circuit is driving a logic low signal on the bus line, the pull-down switch is enabled so that the bus line voltage is pulled down, while the pull-up switch is disabled to prevent the pull-up switch from pulling up the bus line voltage.Type: GrantFiled: December 17, 2001Date of Patent: June 8, 2004Assignee: Intel CorporationInventors: Marcelo Yuffe, Zelig Wayner, Noam Yosef
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Publication number: 20040051555Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.Type: ApplicationFiled: August 18, 2003Publication date: March 18, 2004Inventors: Jeffrey R. Wilcox, Noam Yoset, Marcelo Yuffe
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Patent number: 6633178Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.Type: GrantFiled: September 28, 2001Date of Patent: October 14, 2003Assignee: Intel CorporationInventors: Jeffrey R. Wilcox, Noam Yosef, Marcelo Yuffe
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Publication number: 20030126377Abstract: For one embodiment, a computer system includes both high power and low power buses coupling a processor to a controller. When the processor is in a high power mode, its cache is snooped by the controller via the high power bus. When the processor is in a low power mode, its cache is snooped by the controller via the low power bus.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Inventors: Doron Orenstien, Marcelo Yuffe
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Publication number: 20030112751Abstract: A circuit for driving and receiving signals on a bus line includes a pull-up switch and a pull-down switch. The pull-up switch has an impedance that matches the characteristic impedance of the bus line. The pull-down switch has an impedance of about half of the characteristic impedance of the bus line. When the circuit is receiving a signal or driving a logic high signal on the bus line, the pull-up switch is enabled so that the bus line voltage is pulled up, while the pull-down switch is disabled to prevent the pull-down switch from pulling down the bus line voltage. When the circuit is driving a logic low signal on the bus line, the pull-down switch is enabled so that the bus line voltage is pulled down, while the pull-up switch is disabled to prevent the pull-up switch from pulling up the bus line voltage.Type: ApplicationFiled: December 17, 2001Publication date: June 19, 2003Inventors: Marcelo Yuffe, Zelig Wayner, Noam Yosef
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Publication number: 20030062926Abstract: A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Jeffrey R. Wilcox, Noam Yosef, Marcelo Yuffe