Patents by Inventor Marcio T. Oliveira

Marcio T. Oliveira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8429661
    Abstract: Systems and methods storing data for multi-threaded processing permit multiple execution threads to store data in a single first-in first-out (FIFO) memory. Threads are assigned to classes, with each class including one or more threads. Each class may be allocated dedicated entries in the FIFO memory. A class may also be allocated shared entries in the FIFO memory. The shared entries may be used by any thread. Data for a first thread may be stored in the FIFO memory while data for a second thread is read from the FIFO memory, even when the first thread and the second thread are not in the same class. The FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: April 23, 2013
    Assignee: Nvidia Corporation
    Inventors: Robert A. Alfieri, Marcio T. Oliveira
  • Patent number: 8201172
    Abstract: Systems and methods storing data for multi-threaded processing permit multiple execution threads to store data in a single first-in first-out (FIFO) memory. Threads are assigned to classes, with each class including one or more threads. Each class may be allocated dedicated entries in the FIFO memory. A class may also be allocated shared entries in the FIFO memory. The shared entries may be used by any thread. Data for a first thread may be stored in the FIFO memory while data for a second thread is read from the FIFO memory, even when the first thread and the second thread are not in the same class. The FIFO memory may include a speculative read and a speculative write capability. The FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: June 12, 2012
    Assignee: NVIDIA Corporation
    Inventors: Marcio T. Oliveira, Robert A. Alfieri
  • Patent number: 7756148
    Abstract: Systems and methods for generating synthesizable code representing first-in first-out (FIFO) memories may be used to produce FIFO memories for multi-threaded processing. A single FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory. A synthesizable code generator produces synthesizable code for a sender interface, storage, receiver interface, and other features that are specified by a programmer. The other features may reduce power consumption or improve timing. The code generator is used to efficiently produce different variations of FIFO memories.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: July 13, 2010
    Assignee: NVIDIA Corporation
    Inventors: Marcio T. Oliveira, Robert A. Alfieri
  • Patent number: 7630389
    Abstract: Systems and methods for generating synthesizable code representing first-in first-out (FIFO) memories may be used to produce FIFO memories for multi-threaded processing. A single FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory. A synthesizable code generator produces synthesizable code for a sender interface, storage, receiver interface, and other features that are specified by a programmer. The other features may reduce power consumption or improve timing. The code generator is used to efficiently produce different variations of FIFO memories.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: December 8, 2009
    Assignee: NVIDIA Corporation
    Inventors: Robert A. Alfieri, Marcio T. Oliveira