Abstract: A control circuit for a switching stage of an electronic converter includes a PWM signal generator that generates a PWM signal to drive the switching stage of the electronic converter. A loop comparator circuit receives the regulated output voltage of the electronic converter and receives a sum signal from an adder circuit. The loop comparator circuit generates a comparison signal having a first or second logic value in response to the regulated output voltage reaching the sum signal or failing to reach the sum signal. The adder circuit generates the sum signal as a sum of a reference voltage and a programmable offset voltage that is generated by a programmable voltage generator based on a digital word signal. A feedback circuit is coupled to the loop comparator circuit and the PWM signal generator, and provides the digital word signal to the programmable voltage generator.

Abstract: In an embodiment a control circuit includes a low-power detection circuit configured to generate a control signal, wherein the low-power detection circuit is, when a driver circuit operates in a high-power mode, configured to determine a first temporal value indicative of a duration of a second phase (T2), detect whether a logic level of a zero current signal changes from a first logic level to a second logic level during the second phase (T2), in response to detecting that the logic level of the zero current signal changes from the first logic level to the second logic level, determine a second temporal value indicative of a time (TZC) elapsed between an instant (t3) when the logic level of the zero current signal changes from the first logic level to the second logic level during the second phase (T2) and the instant (t1) when the second phase (T2) ends, determine whether a ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than a given number threshold value (TH), in

Abstract: In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.

Abstract: A driver circuit includes an input node to receive an input signal for conversion at the output node of a converter, a driver node to provide to a switching power circuit stage in the converter a pulse-width modulated drive signal having an active time, first and second active time generation paths, and a selector circuit coupled to the first and second active time generation paths. The circuit is operable selectively in a first and a second operational mode wherein the driver node receives the pulse-width modulated drive signal having a first active time value generated in the first active time generation path, or a second active time value generated in the second active time generation path. The second active time generation path includes an active time generator network to provide a second active time value with the second active time value adaptively variable to match the first active time value.

Abstract: A driver circuit includes an input node to receive an input signal for conversion at the output node of a converter, a driver node to provide to a switching power circuit stage in the converter a pulse-width modulated drive signal having an active time, first and second active time generation paths, and a selector circuit coupled to the first and second active time generation paths. The circuit is operable selectively in a first and a second operational mode wherein the driver node receives the pulse-width modulated drive signal having a first active time value generated in the first active time generation path, or a second active time value generated in the second active time generation path. The second active time generation path includes an active time generator network to provide a second active time value with the second active time value adaptively variable to match the first active time value.

Abstract: In an embodiment a control circuit includes a low-power detection circuit configured to generate a control signal, wherein the low-power detection circuit is, when a driver circuit operates in a high-power mode, configured to determine a first temporal value indicative of a duration of a second phase (T2), detect whether a logic level of a zero current signal changes from a first logic level to a second logic level during the second phase (T2), in response to detecting that the logic level of the zero current signal changes from the first logic level to the second logic level, determine a second temporal value indicative of a time (TZC) elapsed between an instant (t3) when the logic level of the zero current signal changes from the first logic level to the second logic level during the second phase (T2) and the instant (t1) when the second phase (T2) ends, determine whether a ratio between the second temporal value (TZC) and the first temporal value (T2) is greater than a given number threshold value (TH), in

Abstract: A converter circuit includes an input node for receiving an input signal and an output node for providing a converted output signal to a load, a switching power stage to receive the input signal and an on-off drive signal switching between an on-state and an off-state, and a reactive output network coupled to the switching power stage and configured to provide the converted output signal to the load. The converter circuit comprises a first feedback signal path configured to generate a PWM-modulated control signal for the switching power stage as a function of the converted output signal, and a second feedback signal path including an output variation sensing circuit to generate at least one output variation signal indicative of variations of the converted output signal over time.

Abstract: A converter circuit includes an input node for receiving an input signal and an output node for providing a converted output signal to a load, a switching power stage to receive the input signal and an on-off drive signal switching between an on-state and an off-state, and a reactive output network coupled to the switching power stage and configured to provide the converted output signal to the load. The converter circuit comprises a first feedback signal path configured to generate a PWM-modulated control signal for the switching power stage as a function of the converted output signal, and a second feedback signal path including an output variation sensing circuit to generate at least one output variation signal indicative of variations of the converted output signal over time.

Abstract: A driver circuit includes an input node to receive an input signal for conversion at the output node of a converter, a driver node to provide to a switching power circuit stage in the converter a pulse-width modulated drive signal having an active time, first and second active time generation paths, and a selector circuit coupled to the first and second active time generation paths. The circuit is operable selectively in a first and a second operational mode wherein the driver node receives the pulse-width modulated drive signal having a first active time value generated in the first active time generation path, or a second active time value generated in the second active time generation path. The second active time generation path includes an active time generator network to provide a second active time value with the second active time value adaptively variable to match the first active time value.