Abstract: A method of compiling a sequence of program instructions, a method of parallel execution of a sequence of program instructions and apparatuses and software supporting such methods are disclosed. The sequence of program instructions is analyzed in terms of basic blocks forming a control flow graph and execution paths through that control flow graph are identified. When more than one execution path leads to a given basic block, or when a loop path is found leading from a given basic block back to the same basic block, a potential convergence point may be identified. A convergence marker is added to the computer program associated with the basic blocks identified in this way and then when the program is executed, the convergence markers found are used to trigger a determination of a subset of the multiple execution threads which are executed following that convergence marker.

Abstract: A method of compiling a sequence of program instructions, a method of parallel execution of a sequence of program instructions and apparatuses and software supporting such methods are disclosed. The sequence of program instructions is analysed in terms of basic blocks forming a control flow graph and execution paths through that control flow graph are identified. When more than one execution path leads to a given basic block, or when a loop path is found leading from a given basic block back to the same basic block, a potential convergence point may be identified. A convergence marker is added to the computer program associated with the basic blocks identified in this way and then when the program is executed, the convergence markers found are used to trigger a determination of a subset of the multiple execution threads which are executed following that convergence marker.

Abstract: An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.