Patents by Inventor Marco Hug

Marco Hug has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10902176
    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: January 26, 2021
    Assignee: Synopsys, Inc.
    Inventors: Erdem Cilingir, Srinivasa R Arikati, Weiping Fang, Marco Hug
  • Publication number: 20170004251
    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
    Type: Application
    Filed: June 10, 2016
    Publication date: January 5, 2017
    Inventors: Erdem Cilingir, Srinivasa R. Arikati, Weiping Fang, Marco Hug
  • Patent number: 9384319
    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: July 5, 2016
    Assignee: Synopsys, Inc.
    Inventors: Erdem Cilingir, Srini Arikati, Weiping Fang, Marco Hug
  • Publication number: 20150052490
    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 19, 2015
    Inventors: Erdem Cilingir, Srini Arikati, Weiping Fang, Marco Hug
  • Patent number: 7135255
    Abstract: A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 14, 2006
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Scott J. Bukofsky, John K. DeBrosse, Marco Hug, Lars W. Liebmann, Daniel J. Nickel, Juergen Preuninger
  • Publication number: 20040191638
    Abstract: A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Applicants: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Scott J. Bukofsky, John K. DeBrosse, Marco Hug, Lars W. Liebmann, Daniel J. Nickel, Juergen Preuninger