Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: A multilayer metal supply rings structure of an integrated circuit comprises at least two parallel perimetral metal rails defined in metal layers of different levels, geometrically superposed one to the other. Each rail is constituted by using definition juxtaposed modules, each module defining on a metal layer parallel segments, longitudinally separated by a separation cut, of each rail, superposed rails of said multilayer structure constituting one supply node being electrically interconnected through a plurality of interconnection vias through dielectric isolation layers between different metal levels. A feature of the multilayer metal supply rings structure is that the segments of each of said perimetral metal rails modularly defined on each metal level belong alternately to one and another supply node upon changing the metal level. A process of defining a multilayer metal supply rings structure is also disclosed.

Abstract: A digital circuit for detecting a phase lock condition of a phase locked loop (PLL) circuit includes a pair of counters respectively receiving a digital signal produced by the PLL circuit, and a digital reference signal that is also received by the PLL circuit. A digital comparator is connected to the pair of counters for comparing count values contained therein at an end of a counting cycle, and for generating a first logic signal when the count values are the same and a second logic signal when the count values are different. A resettable memory receives the logic signals generated by the digital comparator and has a capacity sufficient to store a plurality of the logic signals resulting from successive comparisons.

Abstract: A multilayer metal supply rings structure of an integrated circuit comprises at least two parallel perimetral metal rails defined in metal layers of different levels, geometrically superposed one to the other. Each rail is constituted by using definition juxtaposed modules, each module defining on a metal layer parallel segments, longitudinally separated by a separation cut, of each rail, superposed rails of said multilayer structure constituting one supply node being electrically interconnected through a plurality of interconnection vias through dielectric isolation layers between different metal levels. A feature of the multilayer metal supply rings structure is that the segments of each of said perimetral metal rails modularly defined on each metal level belong alternately to one and another supply node upon changing the metal level. A process of defining a multilayer metal supply rings structure is also disclosed.

Abstract: A digital circuit for detecting a phase lock condition of a phase locked loop (PLL) circuit includes a pair of counters respectively receiving a digital signal produced by the PLL circuit, and a digital reference signal that is also received by the PLL circuit. A digital comparator is connected to the pair of counters for comparing count values contained therein at an end of a counting cycle, and for generating a first logic signal when the count values are the same and a second logic signal when the count values are different. A resettable memory receives the logic signals generated by the digital comparator and has a capacity sufficient to store a plurality of the logic signals resulting from successive comparisons.