Patents by Inventor Marco Passerini
Marco Passerini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240166453Abstract: An orientation device for orienting loose products for a packaging manufacturing line including a conveyor belt movable at a transport speed along an advancement direction between entry and exit stations, a plurality of gripping equipment each including a support body and a gripping head, a transport track to which the support bodies are connected, and wherein the transport track includes an active branch extending parallel to the conveyor belt, spaced from the conveyor belt and completely contained between the entry and exit stations. Each gripping head is rotatable about a rotation axis perpendicular to the conveyor belt and configured to pick up and hold a product transported by the conveyor belt. Each support body is movable parallel to the rotation axis of the respective gripping head between an approached condition and a distanced condition. Each support body moves along the active branch with a speed equal to the transport speed.Type: ApplicationFiled: November 20, 2023Publication date: May 23, 2024Inventors: Mauro VAROTTO, Mauro PASSERINI, Andrea GUIDETTI, Marco ZECCHI
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Patent number: 11936295Abstract: A charge pump circuit is provided, comprising: a first charge pump having an input terminal for receiving a supply voltage and configured to boost the received supply voltage to provide at an output terminal of the first charge pump a first charge pump voltage; a second charge pump having an input terminal coupled to the output terminal of the first charge pump for receiving the first charge pump voltage and configured to boost the received first charge pump voltage to provide at an output terminal of the second charge pump a second charge pump voltage, and a voltage drop sensing device configured to detect drops in the first charge pump voltage and to deactivate second transistors of bypass units associated to the disabled charge pump stages when a drop in the first charge pump voltage is detected.Type: GrantFiled: January 17, 2023Date of Patent: March 19, 2024Assignee: SK hynix Inc.Inventors: Giovanni Bellotti, Miriam Sangalli, Lorenzo Bonuccelli, Marco Passerini
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Publication number: 20230402916Abstract: A charge pump circuit is provided, comprising: a first charge pump having an input terminal for receiving a supply voltage and configured to boost the received supply voltage to provide at an output terminal of the first charge pump a first charge pump voltage; a second charge pump having an input terminal coupled to the output terminal of the first charge pump for receiving the first charge pump voltage and configured to boost the received first charge pump voltage to provide at an output terminal of the second charge pump a second charge pump voltage, and a voltage drop sensing device configured to detect drops in the first charge pump voltage and to deactivate second transistors of bypass units associated to the disabled charge pump stages when a drop in the first charge pump voltage is detected.Type: ApplicationFiled: January 17, 2023Publication date: December 14, 2023Applicant: SK hynix Inc.Inventors: Giovanni BELLOTTI, Miriam SANGALLI, Lorenzo BONUCCELLI, Marco PASSERINI
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Patent number: 11829174Abstract: Disclosed herein is a regulator for a non-volatile memory. The regulator comprises a high voltage supply terminal, a low voltage supply terminal, an output terminal, a ground terminal and an internal node. The regulator further comprises an input amplifier inserted between the low voltage supply terminal and the ground terminal and outputting a first output voltage at a first intermediate output node according to a reference voltage and a feedback voltage provided at its negative and positive input terminals, respectively; a mirror circuit forming two current paths between the internal node and the ground terminal and between the internal node and a second intermediate output node respectively; and a cascode block coupled between the high voltage supply terminal and the internal node and operating in response to a voltage at the second intermediate output node of the regulator where the two current path is formed by the mirror circuit.Type: GrantFiled: August 5, 2021Date of Patent: November 28, 2023Assignee: SK hynix Inc.Inventors: Andrea Grande, Marco Passerini, Stefano Malacrida
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Patent number: 11797039Abstract: A non-volatile memory device comprises memory cells, a first regulator, a second regulator, a first switch, a second switch and capacitor coupling switches. The first regulator comprises a first capacitor, and generates a first voltage at a first node connected to a first subset of the memory cells, to provide the first voltage to the first subset. The second regulator comprises a second capacitor, and generates a second voltage at a second node. The first switch selectively couples the second node to a second subset of the memory cells, to provide the second voltage to the second subset. The second switch selectively couples the first node to the second subset to also provide the first voltage to the second subset. The capacitor coupling switches selectively couple the second capacitor in parallel to the first capacitor when the first switch is deactivated, and the second switch is activated.Type: GrantFiled: April 29, 2022Date of Patent: October 24, 2023Assignee: SK hynix Inc.Inventors: Giovanni Bellotti, Marco Passerini
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Publication number: 20230176601Abstract: A memory device comprises memory cells, a first regulator, a second regulator, a first switch, a second switch and capacitor coupling switches. The first regulator comprises a first capacitor, and generates a first voltage at a first node connected to a first subset of the memory cells, to provide the first voltage to the first subset. The second regulator comprises a second capacitor, and generates a second voltage at a second node. The first switch selectively couples the second node to a second subset of the memory cells, to provide the second voltage to the second subset. The second switch selectively couples the first node to the second subset to also provide the first voltage to the second subset. The capacitor coupling switches selectively couple the second capacitor in parallel to the first capacitor when the first switch is deactivated, and the second switch is activated.Type: ApplicationFiled: April 29, 2022Publication date: June 8, 2023Inventors: Giovanni BELLOTTI, Marco PASSERINI
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Patent number: 11437907Abstract: Disclosed herein is a charge pump architecture in which boosting capacitors of adjacent stages are connected only by NMOS type transistors and comprising a first stage receiving a first voltage and outputting an internal voltage; a second stage receiving the internal voltage and outputting a second voltage at an output terminal, and an auxiliary stage connected to the output terminal, the first stage and second stage including a first type of MOS transistors transferring the voltage from input node internal boosting nodes and being cross-coupled; a second type of MOS transistors with their gate biased by a third type of MOS transistors and fourth type of MOS transistors; the third type of MOS transistors connecting the gate of the second type of MOS transistors; and the fourth type of MOS transistors connecting the gate of the second type of MOS transistors.Type: GrantFiled: August 30, 2021Date of Patent: September 6, 2022Assignee: SK hynix Inc.Inventors: Onur Aker, Marco Passerini
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Patent number: 11430519Abstract: A switching architecture provides input voltage signals from input voltage lines to a plurality of global word lines connected to word lines of a memory array in a memory device. The switching architecture includes a first switching block receiving a first set of positive voltages used to bias unselected word lines and being connected to a first output line providing a first output bias voltage, and a second switching block receiving a second set of positive voltages and a third set of negative voltages used to bias selected word lines and being connected to a second output line providing a second output bias voltage. A plurality of final switches are input connected to the first and second output lines and are output connected to a respective global word line.Type: GrantFiled: March 9, 2021Date of Patent: August 30, 2022Assignee: SK hynix Inc.Inventors: Marco Passerini, Giulio Maria Iadicicco, Yong Tae Kim, Moon Soo Sung, Dario Melchionni, Miriam Sangalli
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Publication number: 20220253083Abstract: Disclosed herein is a regulator for a non-volatile memory. The regulator comprises a high voltage supply terminal, a low voltage supply terminal, an output terminal, a ground terminal and an internal node. The regulator further comprises an input amplifier inserted between the low voltage supply terminal and the ground terminal and outputting a first output voltage at a first intermediate output node according to a reference voltage and a feedback voltage provided at its negative and positive input terminals, respectively; a mirror circuit forming two current paths between the internal node and the ground terminal and between the internal node and a second intermediate output node respectively; and a cascode block coupled between the high voltage supply terminal and the internal node and operating in response to a voltage at the second intermediate output node of the regulator where the two current path is formed by the mirror circuit.Type: ApplicationFiled: August 5, 2021Publication date: August 11, 2022Inventors: Andrea GRANDE, Marco PASSERINI, Stefano MALACRIDA
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Publication number: 20220255423Abstract: Disclosed herein is a charge pump architecture in which boosting capacitors of adjacent stages are connected only by NMOS type transistors and comprising a first stage receiving a first voltage and outputting an internal voltage; a second stage receiving the internal voltage and outputting a second voltage at an output terminal, and an auxiliary stage connected to the output terminal, the first stage and second stage including a first type of MOS transistors transferring the voltage from input node internal boosting nodes and being cross-coupled; a second type of MOS transistors with their gate biased by a third type of MOS transistors and fourth type of MOS transistors; the third type of MOS transistors connecting the gate of the second type of MOS transistors; and the fourth type of MOS transistors connecting the gate of the second type of MOS transistorsType: ApplicationFiled: August 30, 2021Publication date: August 11, 2022Inventors: Onur AKER, Marco PASSERINI
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Publication number: 20210287747Abstract: A switching architecture provides input voltage signals from input voltage lines to a plurality of global word lines connected to word lines of a memory array in a memory device. The switching architecture includes a first switching block receiving a first set of positive voltages used to bias unselected word lines and being connected to a first output line providing a first output bias voltage, and a second switching block receiving a second set of positive voltages and a third set of negative voltages used to bias selected word lines and being connected to a second output line providing a second output bias voltage. A plurality of final switches are input connected to the first and second output lines and are output connected to a respective global word line.Type: ApplicationFiled: March 9, 2021Publication date: September 16, 2021Applicant: SK hynix Inc.Inventors: Marco Passerini, Giulio Maria Iadicicco, Yong Tae KIM, Moon Soo SUNG, Dario Melchionni, Miriam Sangalli
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Patent number: 10171098Abstract: Disclosed herein is an analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising a first node of the input analog voltage; nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.Type: GrantFiled: November 20, 2017Date of Patent: January 1, 2019Assignee: SK Hynix Inc.Inventors: Luigi Paone, Marco Passerini
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Publication number: 20180145698Abstract: Disclosed herein is an analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising a first node of the input analog voltage: nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.Type: ApplicationFiled: November 20, 2017Publication date: May 24, 2018Inventors: Luigi PAONE, Marco PASSERINI
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Patent number: 9909931Abstract: A temperature sensor includes a first current generating circuit configured to generate a first current being constant regardless of temperature changes, a cascode circuit configured to generate a cascode voltage, a second current generating circuit configured to generate a second current being in inverse proportion to temperature, and a compensated voltage output circuit configured to output a compensated voltage having various temperature coefficients in response to the first current and the second current.Type: GrantFiled: April 24, 2015Date of Patent: March 6, 2018Assignee: SK HYNIX INC.Inventors: Kyu Tae Park, Marco Passerini
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Patent number: 9571092Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.Type: GrantFiled: February 3, 2012Date of Patent: February 14, 2017Assignee: Longitude Semiconductor S.a.r.l.Inventors: Marco Passerini, Nicola Maglione
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Publication number: 20160146677Abstract: A temperature sensor includes a first current generating circuit configured to generate a first current being constant regardless of temperature changes, a cascode circuit configured to generate a cascode voltage, a second current generating circuit configured to generate a second current being in inverse proportion to temperature, and a compensated voltage output circuit configured to output a compensated voltage having various temperature coefficients in response to the first current and the second current.Type: ApplicationFiled: April 24, 2015Publication date: May 26, 2016Inventors: Kyu Tae PARK, Marco PASSERINI
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Patent number: 8884666Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.Type: GrantFiled: August 2, 2011Date of Patent: November 11, 2014Assignee: PS4 Luxco S.a.r.l.Inventors: Marco Passerini, Stefano Surico
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Patent number: 8779811Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.Type: GrantFiled: August 2, 2011Date of Patent: July 15, 2014Inventors: Marco Passerini, Stefano Surico
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Patent number: 8644079Abstract: Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.Type: GrantFiled: May 10, 2011Date of Patent: February 4, 2014Inventors: Marco Passerini, Simone Bartoli, Osama Khouri
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Publication number: 20130200941Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.Type: ApplicationFiled: February 3, 2012Publication date: August 8, 2013Applicant: Elpida Memory, Inc.Inventors: Marco Passerini, Nicola Maglione