Patents by Inventor Marco Y. Wirasinghe

Marco Y. Wirasinghe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for streaming multimedia over packet networks
    Patent number: 7106757
    Abstract: A data transmission method and protocol includes progressive coding of a data set into time stamped data packets. The packets are ordered in importance, with some packets being more critical to received data quality than other packets from the same source. If packets are delayed in transit from a source to a receiver, packets of lesser importance are discarded after a set time, a transmission and decoding of a second set of time critical data begins.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventors: Jiang Hong, Igor V. Kozintsev, Marco Y. Wirasinghe
  • System and method for dynamic power management using data buffer levels
    Patent number: 6865653
    Abstract: A power management system for digital circuitry uses data buffer monitoring to determine appropriate processor clock speed or voltage. This allows a processor to be switched from a low power state to a high power state when a monitored data buffer level feeding data to a power intensive application is greater than a second memory buffer level. The processor is switched from a high power state to a low power state when the monitored data buffer level is less than a first memory buffer level.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: March 8, 2005
    Assignee: Intel Corporation
    Inventors: André Zaccarin, Trevor Pering, Marco Y. Wirasinghe
  • System and method for streaming multimedia over packet networks
    Publication number: 20030112822
    Abstract: A data transmission method and protocol includes progressive coding of a data set into time stamped data packets. The packets are ordered in importance, with some packets being more critical to received data quality than other packets from the same source. If packets are delayed in transit from a source to a receiver, packets of lesser importance are discarded after a set time, a transmission and decoding of a second set of time critical data begins.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 19, 2003
    Inventors: Jiang Hong, Igor V. Kozintsev, Marco Y. Wirasinghe
  • Data driven power management
    Publication number: 20030115428
    Abstract: A power management system for digital circuityr uses data buffer monitoring to determine appropriate processor clock speed or voltage. This allows a processor to be switched from a low power state to a high power state when a monitored data buffer level feeding data to a power intensive application is greater than a second memory buffer level. The processor is switched from a high power state to a low power state when the monitored data buffer level is less than a first memory buffer level.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 19, 2003
    Inventors: Andre Zaccarin, Trevor Pering, Marco Y. Wirasinghe