Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semiconductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.

Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semi-conductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.

Abstract: A method is disclosed of manufacturing an integrated circuit. The method comprises providing a substrate (100) comprising a source region (102) and a drain region (104) separated by a channel region (106, 406), said channel region being covered by a gate stack separated from the channel region by a dielectric layer (110), the gate stack comprising a metal portion (112) over the dielectric layer (110) and a polysilicon portion (116) over the metal portion (112); implanting an oxide reducing dopant (130) into the polysilicon portion (116); depositing a silicidation metal (140) over the implanted polysilicon portion (116); and converting the implanted polysilicon portion (116) into a suicide portion. By fully converting the polysilicon portion (116) into a suicide portion, the dopant (130) is ‘snow-ploughed’ towards the interface between the metal portion (112) and the polysilicon portion (116) where it reacts with any oxide formed at said interface.

Abstract: A method of manufacturing a semiconductor device having gate electrodes of a suitable work function material is disclosed. The method comprises providing a substrate (100) including a number of active regions (110, 120) and a dielectric layer (130) covering the active regions (110, 120), and forming a stack of layers (140, 150, 160) over the dielectric layer. The formation of the stack of layers comprises depositing a first metal layer (140), having a first thickness, e.g.