Abstract: A computer system apparatus is disclosed for improved handling of requests by a peripheral device for data from memory. The apparatus serially receives multiple memory addresses from which data is requested by the peripheral device, and makes a determination that the received addresses form a sequence in memory. Upon this determination, the apparatus begins prefetching data from addresses anticipated to be received from the peripheral device, as an extension of the address sequence received. This prefetching of data, without waiting for an anticipated address to actually be received from the peripheral device, permits the apparatus of the invention to be simultaneously performing reads to memory and communication with the requesting peripheral device. This decreases the access time on the peripheral bus, providing increased bus rates and thereby improving computing throughput.

Abstract: An improvement is disclosed for a computer system wherein a high speed peripheral device sends data words of a first length to a memory which operates with a word of a greater length, for example, twice the data word length. The improvement includes an apparatus for identifying pairs of data words which belong together in a single memory word. Then, a pair of the data words can be written to memory in a single operation, rather than two separate write operations.