Abstract: A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.

Abstract: A system and method for default data forwarding coherent caching agent is present. A node controller receives a cache line request from either a local caching agent (local processor) or from a remote node controller. When a node controller receives a request from a local caching agent, the node controller sends the corresponding cache line to the local caching agent, all the while maintaining cache line forward state control. When the node controller receives a request from a remote node controller, the node controller sends the cache line, along with the cache line forward state control, to the remote node controller. In addition, the node controller performs particular actions based upon the source of the cache line request, the request type, and the cache line current status.

Abstract: A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.