Patents by Inventor Mari Otsuka
Mari Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230092162Abstract: An insulating device includes: a first inductor including a first coil layer located in a first plane; a second inductor separated from the first inductor, the second inductor including a second coil layer located in the first plane, a central axis of the second coil layer being positioned inside the first coil layer; and an insulating layer located between the first inductor and the second inductor.Type: ApplicationFiled: March 4, 2022Publication date: March 23, 2023Inventors: Tatsuya OHGURO, Kenichi OOTSUKA, Mari OTSUKA, Akira ISHIGURO, Masaki YAMADA
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Patent number: 8778778Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: GrantFiled: August 18, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Publication number: 20120049312Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: ApplicationFiled: August 18, 2011Publication date: March 1, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumasa TANIDA, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Patent number: 8053268Abstract: A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si—H concentration is smaller than N—H concentration.Type: GrantFiled: October 28, 2008Date of Patent: November 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Mari Otsuka, Hiroyuki Kamijiyo, Hideaki Harakawa
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Publication number: 20110248368Abstract: A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si—H concentration is smaller than N—H concentration.Type: ApplicationFiled: June 17, 2011Publication date: October 13, 2011Inventors: Mari OTSUKA, Hiroyuki Kamijiyo, Hideaki Harakawa
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Publication number: 20090108388Abstract: A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si—H concentration is smaller than N—H concentration.Type: ApplicationFiled: October 28, 2008Publication date: April 30, 2009Inventors: Mari OTSUKA, Hiroyuki Kamijiyo, Hideaki Harakawa
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Publication number: 20040211958Abstract: A semiconductor device having a conductive layer comprising: a semiconductor substrate; a first interlayer insulating film formed above the semiconductor substrate; a first conductive layer formed in the first interlayer insulating film; a second interlayer insulating film formed on the first interlayer insulating film and the first conductive film; a contact that is formed in the second interlayer insulating film, an one end of the contact being electrically connected to the first conductive layer; a second conductive layer formed on the second interlayer insulting film and the contact; and a dummy pattern formed in the first conductive layer and adjacent to the one end of the contact, an upper surface of the dummy pattern reaching a lower surface of the second interlayer insulating film that is formed on the first conductive layer, and the lower surface of the dummy pattern reaching the first interlayer insulating film that is formed under the first conductive layer.Type: ApplicationFiled: October 14, 2003Publication date: October 28, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideki Osamura, Mari Otsuka, Tadashi Matsuno
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Patent number: 6180513Abstract: Disclosed are an apparatus and a method for manufacturing a semiconductor device. A Si wafer set within an L/UL chamber is transferred under the state of a high vacuum through a transfer chamber into a Ti chamber. The wafer is heated to at least 300° C. within the Ti chamber by a heating mechanism arranged within the Ti chamber. Then, a TiSix film is formed at a bottom portion of a contact hole by a plasma CVD method using an Ar gas supplied through a gas line as a carrier gas and a TiCl4 gas supplied through another gas line as a source gas, Ti in the source gas being self-aligned with Si in the wafer. The wafer having the TiSix film formed therein is transferred through the transfer chamber into a W chamber without being exposed to the air atmosphere. Within the W chamber, a W film is consecutively deposited by a selective CVD method on the TiSix film.Type: GrantFiled: August 12, 1997Date of Patent: January 30, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Mari Otsuka, Kenichi Otsuka
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Patent number: 5834367Abstract: In a method of manufacturing a semiconductor device having a multilayer wiring structure, it has at least two underlying layers having different etching conditions. Firstly, the native oxide film formed on one of the underlying layers, or a barrier metal layer, is etched out under etching conditions suitable for the barrier metal layer. Then, the surface of the barrier metal layer is capped with a plugging material having etching conditions similar to or substantially the same as those of the other one of the underlying layers, or a lower wiring layer. Subsequently, the native oxide film and the etching by-product formed on the lower wiring layer are etched out under etching conditions suitable for the lower wiring layer. Thereafter, contact holes for the two underlying layers are buried with a conductive substance to establish electric connection with their respective upper conductive layers.Type: GrantFiled: April 12, 1996Date of Patent: November 10, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Mari Otsuka, Kenichi Otsuka
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Patent number: 5607878Abstract: An inter-level insulation film is formed on a first-level interconnection layer and part of the inter-level insulation film which lies on the first-level interconnection layer is etched to form a contact hole. After a natural oxidation film formed on the surface of part of the first-level interconnection layer which is exposed in the contact hole is removed, the resultant structure is exposed to a gas atmosphere containing halogen to purify the surface of the inter-level insulation film. After this, a contact plug is deposited and formed on the first-level interconnection layer which is exposed in the contact hole by the selective CVD method to fill in the contact hole. A second-level interconnection layer is formed on the inter-level insulation film and the first-level and second-level interconnection layers are electrically connected to each other via the contact plug.Type: GrantFiled: September 12, 1995Date of Patent: March 4, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Mari Otsuka, Tomonori Kitakura, Kenichi Otsuka, Kazuya Mori
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Patent number: 4849512Abstract: Derivatives of 3-acylamino-3-deoxyallose represented by the following formula: ##STR1## wherein R.sup.1, R.sup.2, R.sup.3 and R.sup.4 may be hydrogen atoms, or R.sup.1 and R.sup.2, and R.sup.3 and R.sup.4 may be in combination an isopropylidene group, R.sup.5 represents a hydrogen atom or alkyl group, and R.sup.6 represents a hydrogen atom or acyl group, are disclosed. One of the typical compound 3-deoxy-3-(3-tetradecanoyloxytetradecanoylamino)-1,2:5,6-di-O-isopropylide ne- .alpha.-D-allofuranose is prepared by reacting 3-tetradecanoyloxytetradecanoic acid and 3-amino-3-deoxy-1,2:5,6-di-O-isopropylidene-.alpha.-D-allofuranose in the presence of N,N'-dicyclohexylcarbodiimide, as a dehydrating agent. The compound has an excellent carcinostatic activity.Type: GrantFiled: April 1, 1988Date of Patent: July 18, 1989Assignee: SS Pharmaceutical Co., Ltd.Inventors: Minoru Tokizawa, Mari Otsuka, Kazuhiko Irinoda, Seiji Ishizeki, Fumio Ishii, Kenichi Kukita, Hideaki Matsuda, Tatsuhiko Katori