Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).

Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).

Abstract: According to an aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface, a semiconductor die coupled to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, where at least a portion of the first surface is exposed through the molding such that the substrate is configured to function as a heat sink.

Abstract: A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.

Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).

Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include one or more semiconductor die that are electrically coupled with the substrate and the leadframe portions.

Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.

Abstract: According to an aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface, a semiconductor die coupled to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, where at least a portion of the first surface is exposed through the molding such that the substrate is configured to function as a heat sink.

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.