Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A semiconductor device includes first and second cell trench structures extending from a first surface into a semiconductor body, a first semiconductor mesa separating the cell trench structures. The first cell trench structure includes a first buried electrode and a first insulator layer. A first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa. The first semiconductor mesa includes a source zone of a first conductivity type directly adjoining the first surface. The semiconductor device further includes a capping layer on the first surface and a contact structure having a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode. A lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.

Abstract: A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration. A pn-junction between the semiconductor auxiliary region and the semiconductor region is positioned as deep or deeper in the semiconductor region as a pn-junction between the semiconductor channel region and the semiconductor region. The semiconductor auxiliary region is positioned closer to the semiconductor channel region than any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

Abstract: A semiconductor mesa is formed in a semiconductor layer between a first cell trench structure and a second cell trench structure extending from a first surface into the semiconductor layer. An opening is formed in a capping layer formed on the first surface, wherein the opening exposes at least a portion of the semiconductor mesa. Through the opening impurities of a first conductivity type are introduced into the exposed portion of the semiconductor mesa. A recess defined by the opening is formed.

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Abstract: A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.

Abstract: A semiconductor mesa is formed in a semiconductor layer between a first cell trench structure and a second cell trench structure extending from a first surface into the semiconductor layer. An opening is formed in a capping layer formed on the first surface, wherein the opening exposes at least a portion of the semiconductor mesa. Through the opening impurities of a first conductivity type are introduced into the exposed portion of the semiconductor mesa. A recess defined by the opening is formed.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract: A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.