Patents by Inventor Maria Cristina Estacio
Maria Cristina Estacio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230402350Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).Type: ApplicationFiled: August 24, 2023Publication date: December 14, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erwin Ian Vamenta ALMAGRO, Maria Clemens Ypil QUINONES, Romel N. MANATAD, Maria Cristina ESTACIO, Elsie Agdon CABAHUG
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Patent number: 11791247Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).Type: GrantFiled: July 7, 2021Date of Patent: October 17, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erwin Ian Vamenta Almagro, Maria Clemens Ypil Quinones, Romel N. Manatad, Maria Cristina Estacio, Elsie Agdon Cabahug
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Patent number: 11735508Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: November 4, 2021Date of Patent: August 22, 2023Assignee: SEMICONDUCTOR COMONENTS INDUTRIES, LLCInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Publication number: 20230207411Abstract: A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.Type: ApplicationFiled: February 22, 2023Publication date: June 29, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina ESTACIO, Jerome TEYSSEYRE, Elsie Agdon CABAHUG
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Patent number: 11621203Abstract: A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.Type: GrantFiled: August 13, 2019Date of Patent: April 4, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina Estacio, Jerome Teysseyre, Elsie Agdon Cabahug
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Publication number: 20230075519Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Maria Cristina ESTACIO, Seungwon IM
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Patent number: 11545421Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.Type: GrantFiled: January 28, 2021Date of Patent: January 3, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im
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Publication number: 20220406744Abstract: Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.Type: ApplicationFiled: May 24, 2022Publication date: December 22, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jooyang EOM, Seungwon IM, Maria Cristina ESTACIO, Jerome TEYSSEYRE, Inpil YOO
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Patent number: 11502027Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.Type: GrantFiled: January 28, 2021Date of Patent: November 15, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im
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Patent number: 11296069Abstract: In one general aspect, a device can include a leadframe including at least one of an external input terminal or an external output terminal, an interposer made of an insulating material, and a redistribution layer coupled to the interposer and made of a conductive material. The redistribution layer can include a plurality of traces. The device can also include a semiconductor die disposed between the redistribution layer and the leadframe.Type: GrantFiled: January 8, 2020Date of Patent: April 5, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Elsie Agdon Cabahug, Marie Clemens Ypil Quinones, Maria Cristina Estacio, Romel Nogas Manatad, Chung-Lin Wu, Jerome Teysseyre
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Publication number: 20220102248Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).Type: ApplicationFiled: July 7, 2021Publication date: March 31, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erwin Ian Vamenta ALMAGRO, Maria Clemens Ypil QUINONES, Romel N. MANATAD, Maria Cristina ESTACIO, Elsie Agdon CABAHUG
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Publication number: 20220059443Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina ESTACIO
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Patent number: 11177203Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: February 19, 2019Date of Patent: November 16, 2021Assignee: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Publication number: 20210351099Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina ESTACIO, Elsie Agdon CABAHUG, Romel N. MANATAD
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Patent number: 11088046Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.Type: GrantFiled: June 25, 2018Date of Patent: August 10, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina Estacio, Elsie Agdon Cabahug, Romel N. Manatad
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Publication number: 20210242167Abstract: Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.Type: ApplicationFiled: January 26, 2021Publication date: August 5, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Inpil YOO, Maria Cristina ESTACIO, Jerome TEYSSEYRE, Seungwon IM, JooYang EOM
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Publication number: 20210193561Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include one or more semiconductor die that are electrically coupled with the substrate and the leadframe portions.Type: ApplicationFiled: March 4, 2021Publication date: June 24, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina Estacio, Marlon Bartolo, Maria Clemens Ypil Quinones, Chung-Lin Wu
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Publication number: 20210151367Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.Type: ApplicationFiled: January 28, 2021Publication date: May 20, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im
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Patent number: 10943855Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.Type: GrantFiled: August 14, 2018Date of Patent: March 9, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina Estacio, Marlon Bartolo, Maria Clemens Ypil Quinones, Chung-Lin Wu
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Patent number: 10910297Abstract: In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.Type: GrantFiled: June 3, 2019Date of Patent: February 2, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im