Abstract: A data processing system having processors with large instruction sets comprises a plurality of microprogrammed execution units (EAD, BDP, FPP), which communicate with one another and with a memory (MU) by way of a cache memory (CA). One of the units is an addressing unit (EAD). A second unit is a binary and a decimal calculation unit (BOP). A third unit is a floating point calculation unit (FPP). To permit the units to function autonomously, each unit includes its own command block and synchronizing means to authorize or interrupt the execution of the microprogram defined by the instruction in progress in each unit.

Abstract: A controller for microinstructions grouped into microprogram segments, each of which defines a base of a microprogram segment which is to be executed, includes a bank of addressable base registers. Each register in the bank stores an indication of a base in the memory. Registers in the bank are addressed so that the addressed register derives a signal indicative of the base address. Included are an address register for the memory and an output register for microinstructions read from the memory. The address and output registers respectively have outputs and inputs coupled to an address input and a read output of the memory. An adder has inputs responsive to the base indicating signal of the addressed register and to an output of the memory output register. The adder has an output coupled to an input of the address register. The output of the memory output register is coupled to an input of the means for addressing registers in the register bank to control which register of the base register bank is addressed.