Patents by Inventor Marilyn Jean Lang

Marilyn Jean Lang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6202120
    Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: March 13, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Marilyn Jean Lang, Sridhar Begur, Robert Campbell, Carol Elise Bassett
  • Patent number: 5960450
    Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.
    Type: Grant
    Filed: December 24, 1992
    Date of Patent: September 28, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Marilyn Jean Lang, Sridhar Begur, Robert Campbell, Carol Elise Bassett
  • Patent number: 5732406
    Abstract: A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.
    Type: Grant
    Filed: September 23, 1992
    Date of Patent: March 24, 1998
    Assignee: Hewlett-Packard Company
    Inventors: Carol Elise Bassett, Robert Gregory Campbell, Marilyn Jean Lang, Sridhar Begur