Abstract: Systems, computer instructions and computer-implemented methods are disclosed for implementing space- and time-efficient enumerations. An instance of an enumeration class may be created with a constant, plurality of enumerations. A plurality of objects corresponding to the respective enumerations may be stored in memory along with a lookup table indexed by respective ordinal values of the plurality of enumerations, the lookup table including respective references to the stored objects of the instantiated enumeration class. A reference to an enumeration may be stored in a memory location by storing an ordinal value of the enumeration. A determination may then be made to convert a stored ordinal value to a reference to an object, and responsive to the determination, the ordinal value may be loaded and used as an index into the lookup table to obtain the reference to the object corresponding to the enumeration.

Abstract: A tracing controller may utilize a binary execution trace mechanism to trace execution of compiled application machine code. The tracing controller may initiate hardware tracing to gather control-flow hardware traces of a method executing on a processor configured to generate hardware tracing information. The controller may generate a profile based on the hardware tracing information and initiate re-compiling or re-optimizing of the method in response to determining that the new profile differs from the previous profile. The controller may repeatedly profile and re-optimize a method until profiles for the method stabilize. Profiling and hardware tracing of an application may be selectively enabled or disabled allowing the controller to respond to later phase changes in application execution by re-optimizing, thereby potentially improving overall application performance.

Abstract: Systems, computer instructions and computer-implemented methods are disclosed for implementing space- and time-efficient enumerations. An instance of an enumeration class may be created with a constant, plurality of enumerations. A plurality of objects corresponding to the respective enumerations may be stored in memory along with a lookup table indexed by respective ordinal values of the plurality of enumerations, the lookup table including respective references to the stored objects of the instantiated enumeration class. A reference to an enumeration may be stored in a memory location by storing an ordinal value of the enumeration. A determination may then be made to convert a stored ordinal value to a reference to an object, and responsive to the determination, the ordinal value may be loaded and used as an index into the lookup table to obtain the reference to the object corresponding to the enumeration.

Abstract: Systems, computer instructions and computer-implemented methods are disclosed for implementing space- and time-efficient enumerations. An instance of an enumeration class may be created with a constant, plurality of enumerations. A plurality of objects corresponding to the respective enumerations may be stored in memory along with a lookup table indexed by respective ordinal values of the plurality of enumerations, the lookup table including respective references to the stored objects of the instantiated enumeration class. A reference to an enumeration may be stored in a memory location by storing an ordinal value of the enumeration. A determination may then be made to convert a stored ordinal value to a reference to an object, and responsive to the determination, the ordinal value may be loaded and used as an index into the lookup table to obtain the reference to the object corresponding to the enumeration.

Abstract: A tracing controller may utilize a binary execution trace mechanism to trace execution of compiled application machine code. The tracing controller may initiate hardware tracing to gather control-flow hardware traces of a method executing on a processor configured to generate hardware tracing information. The controller may generate a profile based on the hardware tracing information and initiate re-compiling or re-optimizing of the method in response to determining that the new profile differs from the previous profile. The controller may repeatedly profile and re-optimize a method until profiles for the method stabilize. Profiling and hardware tracing of an application may be selectively enabled or disabled allowing the controller to respond to later phase changes in application execution by re-optimizing, thereby potentially improving overall application performance.

Abstract: A processor may implement position-independent memory addressing by providing load and store instructions that include position-independent addressing modes. A memory address may contain a normalized pointer, where the memory address stores a normalized memory address that, when added to an offset previously determined for memory address, defines another memory address. The position-independent addressing mode may also support invalid memory addresses using a reserved value, where a load instruction providing the position-independent addressing mode may return a NULL value or generate an exception when determining that the stored normalized memory address is equal to the reserved value and where a store instruction providing the position-independent addressing mode may store the reserved value when determining that the memory address is an invalid or NULL memory address.

Abstract: A processor may implement self-relative memory addressing by providing load and store instructions that include self-relative addressing modes. A memory address may contain a self-relative pointer, where the memory address stores a memory offset that, when added to the memory address, defines another memory address. The self-relative addressing mode may also support invalid memory addresses using a reserved offset value, where a load instruction providing the self-relative addressing mode may return a NULL value or generate an exception when determining that the stored offset value is equal to the reserved offset value and where a store instruction providing the self-relative addressing mode may store the reserved offset value when determining that the pointer is an invalid or NULL memory address.

Abstract: A tracing controller may utilize a binary execution trace mechanism to trace execution of compiled application machine code. The tracing controller may initiate hardware tracing to gather control-flow hardware traces of a method executing on a processor configured to generate hardware tracing information. The controller may generate a profile based on the hardware tracing information and initiate re-compiling or re-optimizing of the method in response to determining that the new profile differs from the previous profile. The controller may repeatedly profile and re-optimize a method until profiles for the method stabilize. Profiling and hardware tracing of an application may be selectively enabled or disabled allowing the controller to respond to later phase changes in application execution by re-optimizing, thereby potentially improving overall application performance.

Abstract: A tracing controller may utilize a binary execution trace mechanism to trace execution of compiled application machine code. The tracing controller may initiate hardware tracing to gather control-flow hardware traces of a method executing on a processor configured to generate hardware tracing information. The controller may generate a profile based on the hardware tracing information and initiate re-compiling or re-optimizing of the method in response to determining that the new profile differs from the previous profile. The controller may repeatedly profile and re-optimize a method until profiles for the method stabilize. Profiling and hardware tracing of an application may be selectively enabled or disabled allowing the controller to respond to later phase changes in application execution by re-optimizing, thereby potentially improving overall application performance.

Abstract: A tracing controller may utilize a binary execution trace mechanism to trace execution of compiled application machine code. The tracing controller may initiate hardware tracing to gather control-flow hardware traces of a method executing on a processor configured to generate hardware tracing information. The controller may generate a profile based on the hardware tracing information and initiate re-compiling or re-optimizing of the method in response to determining that the new profile differs from the previous profile. The controller may repeatedly profile and re-optimize a method until profiles for the method stabilize. Profiling and hardware tracing of an application may be selectively enabled or disabled allowing the controller to respond to later phase changes in application execution by re-optimizing, thereby potentially improving overall application performance.

Abstract: A tracing controller may utilize a binary execution trace mechanism to trace execution of compiled application machine code. The tracing controller may initiate hardware tracing to gather control-flow hardware traces of a method executing on a processor configured to generate hardware tracing information. The controller may generate a profile based on the hardware tracing information and initiate re-compiling or re-optimizing of the method in response to determining that the new profile differs from the previous profile. The controller may repeatedly profile and re-optimize a method until profiles for the method stabilize. Profiling and hardware tracing of an application may be selectively enabled or disabled allowing the controller to respond to later phase changes in application execution by re-optimizing, thereby potentially improving overall application performance.

Abstract: A tracing controller may utilize a binary execution trace mechanism to trace execution of compiled application machine code. The tracing controller may initiate hardware tracing to gather control-flow hardware traces of a method executing on a processor configured to generate hardware tracing information. The controller may generate a profile based on the hardware tracing information and initiate re-compiling or re-optimizing of the method in response to determining that the new profile differs from the previous profile. The controller may repeatedly profile and re-optimize a method until profiles for the method stabilize. Profiling and hardware tracing of an application may be selectively enabled or disabled allowing the controller to respond to later phase changes in application execution by re-optimizing, thereby potentially improving overall application performance.

Abstract: A garbage collection process performs garbage collection operations in an object-based memory system associated with a processing environment. The garbage collection process receives, at a first garbage collection unit, object references derived from root data from a processor associated with the first garbage collection unit. In addition, the garbage collection process processes, at the first garbage collection unit, the root data received from the processor associated with the first garbage collection unit. The garbage collection process also determines which object references derived from the root data are associated with a second garbage collection unit. Upon determining that an object reference is associated with a second garbage collection unit, the garbage collection process communicates information representative of the object reference to the second garbage collection unit associated with the object reference.

Abstract: A garbage collection process performs garbage collection operations in an object-based memory system associated with a processing environment. The garbage collection process receives, at a first garbage collection unit, object references derived from root data from a processor associated with the first garbage collection unit. In addition, the garbage collection process processes, at the first garbage collection unit, the root data received from the processor associated with the first garbage collection unit. The garbage collection process also determines which object references derived from the root data are associated with a second garbage collection unit. Upon determining that an object reference is associated with a second garbage collection unit, the garbage collection process communicates information representative of the object reference to the second garbage collection unit associated with the object reference.

Abstract: Mechanisms can be used to facilitate suspension of a mutator thread (or mutator threads) while imposing negligible overhead on the mutator computation during periods when thread suspension is not requested. Mechanisms are provided to spill values from a fixed set of resources to a secondary store and to fill values from the secondary store into the fixed set in correspondence with function call triggered overflows and function return triggered underflows. In some configurations, modified spill and/or fill mechanism(s) are used to suspend threads at safe points coinciding with call and/or return sites. Because the modified spill and/or fill mechanism(s) impose negligible overhead when not employed and can be engaged in response to an event (e.g., a start garbage collection event), safe points can be defined at call and/or return points throughout mutator code to reduce the latency between the event and suspension of threads.

Abstract: The analysis of the lifetime of objects in a garbage-collected system may be accomplished quickly and effectively using reference counts and cyclic garbage analysis. A reference count is maintained for each of the objects to indicate the number of incoming pointers. Each time the graph structure is altered, the reference counts are updated. Timestamps are recorded each time the reference count for objects change. If a reference count goes to zero, the corresponding object may be indicated as dead. A garbage collection need only be run once (perhaps at the end), and after it is run the system may indicate which objects are cyclic garbage. The timestamps for objects which are cyclic garbage are then reviewed in reverse chronological order. For each timestamp found, the corresponding object and any object reachable from the corresponding object are indicated as dead. These objects are then removed from the set of cyclic garbage.

Abstract: One embodiment of the present invention provides a system that reduces coherence traffic in a multiprocessor system by supporting both coherent memory accesses and non-coherent memory accesses. During operation, the system receives a request to perform a memory access. Next, the system obtains a page table entry (PTE) associated with the memory access. The system then determines if the memory access is coherent or non-coherent by examining an indicator in the PTE. If the memory access is coherent, the system performs the memory access using a coherence protocol. On the other hand, if the memory access is non-coherent, the system performs the memory access without generating coherence traffic.

Abstract: One embodiment of the present invention provides a system that facilitates garbage collection (GC) in a memory-management system that supports both mark-sweep (MS) objects and reference-counted (RC) objects, wherein both MS objects and RC objects can be marked and have a reference count. During a marking phase of a GC operation, the system first identifies roots for the GC operation. Next, the system marks referents of the roots. The system then recursively traverses referents of the roots which are MS objects and while doing so, marks referents of the traversed MS objects. During a subsequent sweeping phase of the GC operation, the system reclaims objects that are unmarked and have a zero reference count.

Abstract: One embodiment of the present invention provides a memory-management system that supports both address-referenced objects and identifier-referenced objects, wherein an address-referenced object is accessed through a reference containing an address of the object, and wherein an identifier-referenced object is accessed through a reference containing an object identifier (OID) for the object. During operation, the system receives a request to access an object. Next, the system determines if the object is an address-referenced object or an identifier-referenced object. If the object is an address-referenced object, the system accesses the object using the associated address for the object. If the object is an identifier-referenced object, the system accesses the object by using the associated OID for the object to look up the address for the object, and then using the address to access the object.

Abstract: A sampling mechanism is disclosed in which software can specify a property or properties which characterize samples of interest. For example, if the software is interested in cache behavior, the software can specify that information for memory operations, or only information for memory instructions which miss in one or more caches, be reported. The sampling mechanism may specify many such properties and events (properties and events may vary from processor to processor, and may also depend on which properties or events are considered useful for performance analysis).