Patents by Inventor Marites De La Torre

Marites De La Torre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solder bump arrangements for large area analog circuitry
    Patent number: 9343418
    Abstract: An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: May 17, 2016
    Assignee: XILINX, INC.
    Inventors: Donnacha Lowney, Marites De La Torre, Christopher M. Gorman
  • Package integrity monitor with sacrificial bumps
    Patent number: 9128148
    Abstract: An apparatus with package integrity monitoring capability, includes: a package having a die connected to an interposer through a plurality of bumps, wherein at least some of the bumps comprise dummy bumps; a package integrity monitor having a transmitter to transmit a test signal and a receiver to receive the test signal; and a first scan chain comprising a plurality of alternating interconnects in the die and in the interposer connecting some of the dummy bumps in series, wherein the first scan chain has a first end coupled to the transmitter of the package integrity monitor and a second end coupled to the receiver of the package integrity monitor.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 8, 2015
    Assignee: XILINX, INC.
    Inventors: Donnacha Lowney, Marites De La Torre
  • SOLDER BUMP ARRANGEMENTS FOR LARGE AREA ANALOG CIRCUITRY
    Publication number: 20150123265
    Abstract: An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Xilinx, Inc.
    Inventors: Donnacha Lowney, Marites De La Torre, Christopher M. Gorman