Abstract: A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data blocks of write data received in the random access memory of the data storage. A storage controller is communicatively coupled to the random access memory and the data storage and being configured to write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses. A method and processor-implemented process provide for sorting data blocks of write data received in random access memory of data storage. The method and processor-implemented process write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses.

Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.

Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.

Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.

Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

Abstract: Mass storage uses additional error correction codes. The additional codes can be stored in a storage medium (e.g., volatile solid state memory) separate from the associated data. The additional codes may be written to a nonvolatile medium. The additional codes may be transient. The additional codes may be cached. As long as present, the additional codes may be used to correct user data in synch with or in addition to other error detection and correction codes.

Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

Abstract: Mass storage uses additional error correction codes. The additional codes can be stored in a storage medium (e.g., volatile solid state memory) separate from the associated data. The additional codes may be written to a nonvolatile medium. The additional codes may be transient. The additional codes may be cached. As long as present, the additional codes may be used to correct user data in synch with or in addition to other error detection and correction codes.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data blocks of write data received in the random access memory of the data storage. A storage controller is communicatively coupled to the random access memory and the data storage and being configured to write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses. A method and processor-implemented process provide for sorting data blocks of write data received in random access memory of data storage. The method and processor-implemented process write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data blocks of write data received in the random access memory of the data storage. A storage controller is communicatively coupled to the random access memory and the data storage and being configured to write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses. A method and processor-implemented process provide for sorting data blocks of write data received in random access memory of data storage. The method and processor-implemented process write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.

Abstract: A unified debug system with multiple user-configurable trace volumes is disclosed, including embodiments as a system, a method, and a computer-readable medium. Embodiments of the present invention provide more robust and flexible solutions for introducing configurable trace volumes to firmware, allowing a user to specify firmware system configurations for trace buffers, trace frames, and trace volumes, and offer other advantages over the prior art. One embodiment of the present invention pertains to a system that includes a firmware component comprising firmware, and a firmware interface communicatively connected to the firmware component. The firmware includes a plurality of trace volumes for storing a plurality of trace entries. The trace volumes are user-configurable through the firmware interface. The plurality of trace volumes includes first, second and third trace volumes. The first trace volume includes storing at least some of the trace entries to a trace buffer in a first volatile memory component.

Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.

Abstract: Data storage systems are provided. Some embodiments of data storage systems include a storage device controller and a plurality of storage devices. The plurality of storage devices are illustratively in a redundancy scheme and the storage device controller receives from the plurality of storage devices a plurality of symbols. In one embodiment, each of the plurality of symbols is representative of data in the redundancy scheme, and the storage device controller verifies the consistency of the redundancy scheme based at least in part on the plurality of symbols.

Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.

Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

Abstract: In general, this disclosure is directed to techniques for adjusting the timing of operations for a storage device. According to one aspect of the disclosure, a method includes receiving, with at least one device, a workload indicator. The method further includes adjusting, with the at least one device, an operation execution time for the storage device responsive to at least the workload indicator. In some examples, the workload indicator may include a host demand indicator. In additional examples, the workload indicator may include a resource utilization indicator. In further examples, the operation execution time may be one of a write operation execution time or a read operation execution time.