Patents by Inventor Mark A. Kuhlman

Mark A. Kuhlman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11626336
    Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 11, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Daniel Garcia, Kinfegebriel Amera Mengistie, Francesco Carrara, Chang-Ho Lee, Ashish Alawani, Mark Kuhlman, John Jong-Hoon Lee, Jeongkeun Kim, Xiaoju Yu, Supatta Niramarnkarn
  • Publication number: 20210098320
    Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Daniel GARCIA, Kinfegebriel Amera MENGISTIE, Francesco CARRARA, Chang-Ho LEE, Ashish ALAWANI, Mark KUHLMAN, John Jong-Hoon LEE, Jeongkeun KIM, Xiaoju YU, Supatta NIRAMARNKARN
  • Publication number: 20180242455
    Abstract: Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module includes at least one active device stacked on top of an array of passive surface mount components on a substrate. A conductive or non-conductive adhesive can be used to adhere the active device to the array of passive devices.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Inventors: Mark A. KUHLMAN, Anthony James LOBIANCO, Thomas NOLL, Robert W WARREN, Howard E. CHEN
  • Patent number: 9955582
    Abstract: Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module includes at least one active device stacked on top of an array of passive surface mount components on a substrate. A conductive or non-conductive adhesive can be used to adhere the active device to the array of passive devices.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: April 24, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Mark A. Kuhlman, Anthony James LoBianco, Thomas Noll, Robert W. Warren, Howard E. Chen
  • Patent number: 9922937
    Abstract: A self-shielded die includes a substrate, an electronic device attached to the substrate, one or more electrical pads disposed on a bottom surface of the substrate, and an electromagnetic interference (EMI) shield formed of at least one electrically conductive material and connected to ground. At least one of the one or more electrical pads is electrically connected to the electronic device. The EMI shield includes a top shield layer, disposed directly on and substantially completely covering a top surface of the substrate opposite the bottom surface of the substrate, and side shield layers substantially completely covering all sides of the substrate, extending between the top surface of the substrate and the bottom surface of the substrate.
    Type: Grant
    Filed: July 30, 2016
    Date of Patent: March 20, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Mark Kuhlman
  • Publication number: 20180033737
    Abstract: A self-shielded die includes a substrate, an electronic device attached to the substrate, one or more electrical pads disposed on a bottom surface of the substrate, and an electromagnetic interference (EMI) shield formed of at least one electrically conductive material and connected to ground. At least one of the one or more electrical pads is electrically connected to the electronic device. The EMI shield includes a top shield layer, disposed directly on and substantially completely covering a top surface of the substrate opposite the bottom surface of the substrate, and side shield layers substantially completely covering all sides of the substrate, extending between the top surface of the substrate and the bottom surface of the substrate.
    Type: Application
    Filed: July 30, 2016
    Publication date: February 1, 2018
    Inventor: Mark Kuhlman
  • Publication number: 20090267220
    Abstract: Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module includes at least one active device stacked on top of an array of passive surface mount components on a substrate. A conductive or non-conductive adhesive can be used to adhere the active device to the array of passive devices.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 29, 2009
    Inventors: Mark A. Kuhlman, Anthony LoBianco, Thomas Noll, Robert W. Warren
  • Publication number: 20090127695
    Abstract: A substrate pad in a semiconductor package having a geometry and structure that facilitates providing a solder joint to the pad that has enhanced structural integrity and resistance to mechanical impact. The pad may include a plated metal stud that anchors the solder to the pad interface, providing a more compliant solder joint, even when lead-free solder is used.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Inventors: Patrick Kim, Mark A. Kuhlman, Yifan Guo, Anthony LoBianco, Robert W. Warren
  • Publication number: 20080315396
    Abstract: According to an exemplary embodiment, an overmolded semiconductor package includes at least one semiconductor die situated over a package substrate. The overmolded semiconductor package further includes a mold compound overlying the at least one semiconductor die and the package substrate and having a top surface. The overmolded semiconductor package further includes a first patterned conductive layer situated on the top surface of the mold compound. The overmolded semiconductor package can further include at least one conductive interconnect situated in the mold compound, where the at least one conductive interconnect is electrically connected to the first patterned conductive layer. The first patterned conductive layer can include at least one passive component.
    Type: Application
    Filed: May 12, 2008
    Publication date: December 25, 2008
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Mark A. Kuhlman, Anil Agarwal
  • Patent number: 6903270
    Abstract: Method and structure for securing a mold compound to a printed circuit board is disclosed. A through hole or a blind hole is fabricated in a printed circuit board adjacent to a die. The hole is then filled with a mold compound. The mold compound also surrounds and covers the die. The mold compound within the hole locks the mold compound to the surface of the printed circuit board. In one embodiment, a through hole or a blind hole is fabricated adjacent to a semiconductor die. The semiconductor die is attached to a layer of gold-plated copper on the printed circuit board. After the semiconductor die is attached to the layer of gold-plated copper on the printed circuit board, the semiconductor die is surrounded and covered by the mold compound and the fabricated hole is filled with the mold compound. The mold compound within the hole has good adhesion to the resin layer which constitutes the printed circuit board. This adhesion locks the mold compound securely to the surface of the printed circuit board.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: June 7, 2005
    Assignee: Skyworks Solutions, Inc.
    Inventors: Doug A. Hawks, Mark A. Kuhlman, Kevin J. Cote