Abstract: A data stream is converted from a synchronous transfer mode (STM) to an asynchronous transfer mode (ATM) by extracting data of a number of payload signals from the data stream, writing data of the payload signal into a random access memory (RAM), separately recording address locations of the data of each of the payload signals in separate buffers, directing the RAM to separately read the data of the payload signals, and attaching a cell header to the data read from the RAM to form ATM cells.

Abstract: A high capacity packet switch is implemented using an expansion module that divides an incoming packet cell into a plurality of segments and supplies the segments, based on their sequential order, to respective ones of a plurality of concentrator units contained in the expansion module. Each concentrator unit includes a plurality of concentrator logic units and one of those logic units accepts a segment for storage based on routing information contained in the packet cell. The stored segments forming a packet cell are thereafter unloaded and recombined in proper sequence for routing to a packet switch module, which then forwards the packet cell toward its destination.

Abstract: In a duplicate active-standby memory unit arrangement, a resynchronization initiation determination is made on a cell-interval-by-cell-interval basis based on the equality of cell contents of corresponding queues in the active and standby memory units. If an inequality of the cell contents of the corresponding queues in the active and standby memory units occurs during any cell interval, resynchronization may be initiated. In an exemplary embodiment of the invention, the lengths of data in corresponding queues, i.e., the number of cells stored in the corresponding queues, in the active and standby memory units are compared on a cell-interval-by-cell-interval basis. If the number of cells stored in any of the queues is different than the number of cells its corresponding queue in the other of the memory units during any cell interval, resynchronization of the memory units is initiated.

Abstract: In an asynchronous transfer mode (ATM) switching arrangement buffer memory capacity is effectively and efficiently increased by employing a plurality of circuit cards including a master circuit card and a plurality of so-called slave circuit cards including additional buffer memory and an internal cell format in which all of the ATM cell routing information is supplied directly to the master circuit card. Then, the master circuit card utilizes the ATM cell routing information to control writing and reading of data to and from its buffer memory locations and the buffer memory locations of each of the plurality of slave circuit cards. This control of the plurality of slave circuit cards requires only unidirectional communications links to pass the control information from the master circuit card to the slave circuit cards.

Abstract: A shared-buffer-memory-based asynchronous transfer mode (ATM) switch module (1) is duplicated (2) and operates in active-standby mode for fault-tolerance. Following failure and repair of a module, contents of the two modules are resynchronized as follows. When the synchronizing operation is begun contents of the memory of the repaired standby module are cleared, all writes to the active module's memory are also made to the standby module's memory, and the system monitors the overwriting of the contents of the active module's memory that existed at the time the synchronizing commences. This is done by a function (FIG. 4), which sets a flat (64) in a queue-length-counter monitor (60) for every active-module queue-length counter (200) that reaches a count of zero, to indicate that its corresponding buffer-memory queue (100) has been emptied.

Abstract: An m.times.n (m>n) output Packet Switch Unit is implemented by using an n.times.n Packet Switch Module and an m:n Concentrator. The arriving packet cells are supplied from the m Concentrator inputs to the n Concentrator outputs in a "first-in first-out" (FIFO) sequence. The Concentrator provides for buffering of arriving packet cells on the m Concentrator inputs in excess of available packet cell positions in the n Concentrator outputs until they can be supplied to a concentrator output in the FIFO sequence. In turn, packet cells from the n Concentrator outputs are supplied to n inputs of the Packet Switch Module which supplies them to appropriate output destinations associated with the n outputs of the Packet Switch Module. A plurality of the Concentrator-Based output Packet Switch Units is readily employed to implement any "larger" Packet Switch architecture.

Abstract: A shared-buffer-memory-based ATM switching module (FIG. 1) used with ATM cells having a multiplicity of priorities has a plurality of queues (100) for each output port (O-N), one for each cell priority, and handles buffer overflow in a manner fair to all output ports. It initially allows output-port queues (100) to completely consume the buffer memory (12). Thereafter, when an additional incoming cell is received for which there is no room in the buffer memory, the lengths of all of the queues of each output port are individually summed (402) and compared to determine which port has the greatest number of buffered cells (406). A buffered ATM cell is discarded (410) from the lowest-priority non-empty queue of that port (408). The incoming cell is then stored in the memory space vacated by the discarded cell (412).

Abstract: A packet switching arrangement in which packet retransmission is provided by the network for packets found by the network to be unusable. A packet switch node is equipped with a packet path and a control signaling path cooperating with packet address route arbitration and gating circuitry for effecting the packet retransmission. As a packet from a network input unit is passed from switch node to switch node a control signaling path through the switch nodes back to the input unit originating the packet is established. When a switch node detects an unusable packet a retransmit control signal is returned via the control signaling path to the input unit originating the packet. The input unit responds to the retransmit signal by resending the original packet. An unusable packet is blocked from further transmission in one embodiment and marked for removal at the network output ports in another embodiment. Unusable packets result from packet corruption or from packet collision within a switch node.