Abstract: A method and apparatus are provided in which a control scheme is implemented to enable a PCI bus to operate more than two PCI slots into which PCI devices may be installed. The PCI slots are checked to determine if a PCI device is installed in the slots and the speed at which the installed PCI devices are capable of running. If any of the slots has a 33 MHz device installed in any of the slots, the system is enabled to run more than two slots, and all of the PCI devices will run at 33 MHz. When no 33 MHz cards or devices are installed in the PCI slots, and PCI devices are only installed in the first two slots, then the system is enabled to run only the first two slots at the speed of 66 MHz. In one alternative embodiment, a default configuration routine sets the PCI bus speed at one of the operating frequencies and modifies that default if it is determined during a system configuration cycle that another speed is more appropriate.

Abstract: A method and implementing computer system is provided in which PCI CONFIG.sub.-- ADDRESS and CONFIG.sub.-- DATA conventions are maintained in a large computer system and each PCI Host Bridge (PHB) CONFIG.sub.-- ADDRESS register and each PHB CONFIG.sub.-- DATA register have separate and system-unique addresses. In one example, the operating system provides a service to translate the device driver's configuration operation to a particular bus and device in the system, to a particular CONFIG.sub.-- ADDRESS or CONFIG.sub.-- DATA register of the PHB which has that device under it. By using this method, the hierarchical system can use architecture-independent routing of addresses down to the PHB that contains the appropriate CONFIG.sub.-- ADDRESS and CONFIG.sub.-- DATA registers.

Abstract: A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen PCI peripheral component slots to have access through a single PCI host bridge to the system bus.

Abstract: A method of registering a newly added peripheral device with a computer system by responding with a status message from the device to a bus of the computer system, in response to an access attempt, and within a predetermined time period from the deasserting of the reset signal applied to device, so as to avoid stalling and thereby avoid the need to reboot the system in order to initialize the new peripheral device with the operating system. The device may be allowed to initially send a retry response, provided the response occurs during an initial latency period which is less than the predetermined time period. The invention also enables the peripheral device to respond to non-configuration cycles immediately following configuration completion. Internal logic of the peripheral device can be initialized after responding with the status message.

Abstract: A methodology and implementing system 101 are provided in which a PCI bus is enhanced to operate at a plurality of data transfer speeds, including for example, 133 MHz in order to accommodate subsystem boards operating at higher frequencies, while at the same time allowing normal 66 MHz PCI clocking for devices designed to operate at the lower 66 MHz standard PCI speed. Master strobe MSTB 303, 403 and target strobe TSTB signals 309, 411 are generated in a handshaking methodology to determine if a master data transaction requesting device and a target data transaction device are designed to operate at the higher data transfer frequency. Higher frequency capable devices or boards are run at the increased frequency when both the requesting master and the selected target devices request the higher transfer rate, and standard devices or boards are run at the lower standard PCI frequency, while both master and target devices are coupled to and run from the same multi-speed PCI bus 125.

Abstract: A method and system for translating peer-to-peer access across multiple Peripheral Component Interconnect (PCI) host bridges within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. A first and at least a second PCI local buses are also connected to the system bus via a first PCI host bridge and a second PCI host bridge, respectively. The two PCI local buses have bus transaction protocols that are different from those of the system bus. At least one PCI device is connected to each of the two PCI local buses, and shares data with the processor and the system memory. In addition, each PCI device shares data with the other PCI device as peer-to-peer devices across multiple PCI host bridges.

Abstract: The present invention provides a computer system which allows a user to identify which one of a plurality of feature cards has issued an error signal. The device issuing the error signal is then isolated and error recovery techniques, (or re-initialization) are implemented only on the device with the error condition. The computer system includes additional control logic, along with a bridge chip that interconnects different information buses and at least one connector slot for receiving a feature card, which implements specific functions such as I/O, memory, or the like. When it is determined that an error signal is present the system hardware activates and holds a reset signal to the device which issued the error signal. Additionally, a status bit in a register in the bridge chip is set.

Abstract: A method for supporting peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, executing added protocols for the support of PCI peer-to-peer access request across separate PCI host bridges within the data-processing system.

Abstract: A method for preventing peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, denying the access request such that a PCI peer-to-peer access across separate PCI host bridges within a data processing system is prevented.

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uni-processor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queueing of interrupts from many sources, and for queueing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software.

Abstract: A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism.

Abstract: An information handling system includes one or more processors, a system bus or network connecting the processors, a memory system connected to the system bus, an asynchronous signal controller connected to the system bus, one or more I/O bridges connected to the system bus, an I/O bus connected to each I/O bridge, one or more devices connected to the I/O bus, including perhaps another I/O-bus-to-I/O-bus bridge where additional devices may be connected to a second I/O bus, wherein the first or host bridge includes remote interrupt control logic having a register wherein an input to each position in the register is from one of the I/O devices downstream from the host bridge, and a shadow register address buffer, both under the control of a sample circuit connected to outputs of the register such that when a change in any register position is detected by the sample circuit, the entire contents of the register are sent to the shadow register indicated in the shadow register address buffer by a processor bypass t