Abstract: A system and method is described for providing automated sample preparation for plan view transmission electron microscopy. A sample wafer is microcleaved from a semiconductor wafer and mounted on a first support stub. Then the sample wafer is cut with an automated diamond sawing tool to expose a cross sectional view of the sample wafer. The sample wafer is removed from the first support stub and rotated to orient the sample wafer for plan view imaging. The rotated sample wafer is then remounted on a second support stub and cut with the automated diamond sawing tool to expose a plan view surface of the rotated sample wafer. The remounted sample wafer is subsequently prepared for focused ion beam (FIB) milling and plan view transmission electron microscopy imaging.

Abstract: A system and method is described for providing automated sample preparation for plan view transmission electron microscopy. A sample wafer is microcleaved from a semiconductor wafer and mounted on a first support stub. Then the sample wafer is cut with an automated diamond sawing tool to expose a cross sectional view of the sample wafer. The sample wafer is removed from the first support stub and rotated to orient the sample wafer for plan view imaging. The rotated sample wafer is then remounted on a second support stub and cut with the automated diamond sawing tool to expose a plan view surface of the rotated sample wafer. The remounted sample wafer is subsequently prepared for focused ion beam (FIB) milling and plan view transmission electron microscopy imaging.

Abstract: An apparatus, method and system provide for caller input rate control for automatic speech recognition (ASR) components within interactive communication systems. The various embodiments provide a concentrator functionality to increase the capacity of ASR systems, and provide a delay functionality to continue to provide service to callers during congestion or overload conditions. The delay functionality provides various associated delay modes, including the insertion of silent periods within messages or prompts played to a caller, and providing increased message duration. The preferred method embodiment determines a usage level of a plurality of ASR input channels, and when the usage level is greater than a first predetermined threshold, provides an associated delay mode for a message output on an output channel of the plurality of output channels.

Abstract: A rotary motion limiting arrangement includes a stationary component, a rotating component rotatable in opposite directions relative thereto, a pair of stops movably mounted on the stationary component for establishing a first set of opposite limits to rotational movement of the rotating component, and a link fastened to the stops such that, as one stop is moved between extended and retracted positions across and outside of a path of revolution of a lug on the rotating component the other stop is moved oppositely between retracted and extended positions. A braking mechanism is positioned, upon electrical energization, to halt rotation of the rotating component. Switches situated adjacent to the link and rotating component are electrically connected to the braking mechanism for establishing a second set of opposite limits to rotational movement of the rotating component within the limits of the first set.

Abstract: A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.

Abstract: A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations.