Abstract: An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

Abstract: Lateral sleep systems for aircraft are disclosed. A first lateral sleep apparatus is positioned on a first side of a divider adjacent a first seat, the lateral sleep apparatus includes a first headrest and a first cradle. The first cradle supports the first headrest and includes a first panel mounting interface coupling the first headrest to a first support ledge of the divider. A second lateral sleep apparatus is positioned on a second side of the divider adjacent a second seat, where the second lateral sleep apparatus includes a second headrest and a second cradle. The second cradle supports the second headrest and includes a second panel mounting interface coupling the second headrest to a second support ledge of the divider.

Abstract: Lateral sleep systems for aircraft are disclosed. A divider is located between a first seat and a second seat of the aircraft. The divider includes a first panel oriented toward the first seat and a second panel oriented toward the second seat. The first panel defines a first support ledge. The second panel defines a second support ledge. A first lateral sleep apparatus positioned on a first side of the divider adjacent the first seat includes a first headrest and a first cradle. The first cradle supports the first headrest and includes a first panel mounting interface coupling the first headrest to the first support ledge. A second lateral sleep apparatus positioned on a second side of the divider adjacent the second seat includes a second headrest and a second cradle. The second cradle supports the second headrest and includes a second panel mounting interface coupling the second headrest to the second support ledge.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Inductively coupled plasma (ICP) analyzers use an ICP torch to generate a plasma in which a sample is atomized an ionized. Analysis of the atomic ions can be performed by atomic analysis, such as mass spectrometry (MS) or atomic emission spectrometry (AES). Particle based ICP analysis includes analysis of particles such as cells, beads, or laser ablation plumes, by atomizing and ionizing particles in an ICP torch followed by atomic analysis. In mass cytometry, mass tags of particles are analyzed by mass spectrometry, such as by ICP-MS. Systems and methods of the subject application include one or more of: a demountable ICP torch holder assembly, an external ignition device; an ICP load coil comprising an annular fin, particle suspension sample introduction fluidics, and ICP analyzers thereof.

Abstract: Techniques are provided herein for forming thin film transistor structures having a laterally recessed gate electrode. The gate electrode may be recessed such that it does not extend under one or both conductive contacts of the transistor. Recessing the lateral dimensions of the gate electrode can reduce gate leakage current and parasitic capacitance. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. According to some such embodiments, the memory cells are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory cell arrays are formed within the interconnect region. Any of the given TFT structures may include a gate electrode that is laterally recessed such that one or more of the contacts are not directly over the gate electrode.

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

Abstract: Inductively coupled plasma (ICP) analyzers use an ICP torch to generate a plasma in which a sample is atomized an ionized. Analysis of the atomic ions can be performed by atomic analysis, such as mass spectrometry (MS) or atomic emission spectrometry (AES). Particle based ICP analysis includes analysis of particles such as cells, beads, or laser ablation plumes, by atomizing and ionizing particles in an ICP torch followed by atomic analysis. In mass cytometry, mass tags of particles are analyzed by mass spectrometry, such as by ICP-MS. Systems and methods of the subject application include one or more of: a demountable ICP torch holder assembly, an external ignition device; an ICP load coil comprising an annular fin, particle suspension sample introduction fluidics, and ICP analyzers thereof.

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: According to a first embodiment, a feeding bottle comprises a vessel, collar, and nipple. The nipple comprises a base portion, a teat portion, an areola portion allowing movement of the teat portion towards and away from the base portion. According to a second embodiment, a feeding bottle comprises a vessel, collar, nipple and handle portion removeably secured to the vessel by the collar. The invention includes a flexible region or regions to provide a more natural feeding by closely mimicking the human breast.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.