Abstract: A timing based adaptive equalization circuit (10) dynamically monitors a signal received at an input terminal (16) and compensates for attenuation losses in the transmission of the signal by adjusting an equalization value that increases or decreases the equalization of the signal. A digital phase locked loop control circuit (26) centers the transition of the equalized signal in a delay line circuit (31). An analog delay locked loop circuit (29) provides a fixed throughput time for matching delay elements of delay line circuits (31, 41 and 51) in the adaptive equalization circuit (10). Timing signals propagating in the delay line circuits (31, 41 and 51) are stored in sampler circuits (36, 46 and 56). The equalization value for equalizing the input signal is adjusted based on stored logic values of specific storage elements in the sampler circuits (46 and 56).

Abstract: A computer implemented method for generating an integrated circuit design (11) is provided. A description of a circuit (16) is provided in a format such as a Hardware Description Language (12). A functional simulation (17) of the description is run to determine functionality of the circuit. A netlist conversion (18) converts the description to a netlist comprising both a single-ended and differential circuit. The netlist conversion (18) converts the description to a single-ended description (24), replaces single-ended cells with differential cells and interconnects the differential cells (25), and exchanges terminals of the differential cells to maintain logic equivalence (26). A simulation with timing (19) is run on the netlist to verify timing characteristics of the circuit. The netlist is then provided to a router to generate a physical circuit layout (20) having both single-ended and differential circuits.