Abstract: A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, wherein one or more of the instructions reference a defined set of logical registers having multiple addressable sizes as sources and destinations of operands for the instruction. A plurality of physical registers are provided in excess of the number of defined set of logical registers. Physical registers are selectively allocated to one of said defined set of logical registers responsive to an instruction for writing to said one of said logical registers and the size associated with the logical register.

Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away).

Abstract: An exception handling system is used, in an exemplary embodiment, to provide exception handling for prefetched instruction bytes in a pipelined 486-type microprocessor. The microprocessor includes a prefetch unit (22) that controls the loading of a prefetch queue (24), including appending a valid bit to each prefetched instruction byte--this valid bit is conventionally used to notify an instruction decoder (26) that a transferred instruction byte is not valid (such as resulting from a change of flow), causing the decoder to signal a stall condition. According to the exception handling technique of the invention, if the prefetch unit detects that any of a selected number of exception conditions (such as limit violations and page faults) applies to a prefetched instruction byte, it invalidates that instruction byte by clearing the valid bit.

Abstract: A microprocessor has a plurality of input/output pins and processing coupled to the input/output pins. Circuitry is provided for selectively decoupling the processing circuitry with one or more of the input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.

Abstract: A bus precharge circuit is provided that precharges a bus line or node as an inverse function of the precharge level already attained on the bus line, such that the precharge level on the bus line is gradually approached. The precharge circuit charges the bus line to a midpoint between high and low logic states. The preexisting state of the bus line is stored and is used to select one of two voltage supplies to which the bus line may be partially pulled up or down. The switchpoint of a precharge circuit sensing gate is set to be equivalent to the switchpoint of the receiving gate of receiver on the bus line.