Patents by Inventor Mark C. H. Lamorey
Mark C. H. Lamorey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150206835Abstract: An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels.Type: ApplicationFiled: October 13, 2011Publication date: July 23, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark C. H. Lamorey, David B. Stone
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Patent number: 9087805Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.Type: GrantFiled: October 27, 2014Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: James V. Crain, Jr., Mark C. H. Lamorey, Christopher D. Muzzy, Thomas M. Shaw, David B. Stone
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Patent number: 9059552Abstract: Aspects of the present invention relate to land grid array socket cartridge structures. In one embodiment, a land grid array (LGA) cartridge structure includes: a deformable thin film having at least one aperture configured to hold a substantially liquid metal, whereby in a compressed state of the deformable thin film, the substantially liquid metal of the deformable thin film is configured to electro-mechanically couple a carrier and a socket base. Another embodiment includes a method of forming a LGA cartridge structure. The method includes: providing a deformable thin film having a first surface and a second surface, and forming at least one aperture within the deformable thin film through the first surface and the second surface, wherein the aperture is configured to hold a substantially liquid metal.Type: GrantFiled: January 21, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Erwin B. Cohen, Mark C. H. Lamorey
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Patent number: 9057760Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.Type: GrantFiled: January 20, 2011Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Luke D. Lacroix, Mark C. H. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr, Peter Slota, Jr., David B. Stone
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Patent number: 9006739Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.Type: GrantFiled: April 17, 2012Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: James V. Crain, Jr., Mark C. H. Lamorey, Christopher D. Muzzy, Thomas M. Shaw, David B. Stone
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Patent number: 8999846Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.Type: GrantFiled: April 17, 2014Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Publication number: 20150044787Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.Type: ApplicationFiled: October 27, 2014Publication date: February 12, 2015Inventors: James V. Crain, JR., Mark C.H. Lamorey, Christopher D. Muzzy, Thomas M. Shaw, David B. Stone
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Publication number: 20140227874Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.Type: ApplicationFiled: April 17, 2014Publication date: August 14, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luke D. LaCroix, Mark C.H. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
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Patent number: 8796133Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.Type: GrantFiled: July 20, 2012Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Timothy H. Daubenspeck, Mark C. H. Lamorey, Howard S. Landis, Xiao Hu Liu, David L. Questad, Thomas M. Shaw, David B. Stone
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Publication number: 20140206206Abstract: Aspects of the present invention relate to land grid array socket cartridge structures. In one embodiment, a land grid array (LGA) cartridge structure includes: a deformable thin film having at least one aperture configured to hold a substantially liquid metal, whereby in a compressed state of the deformable thin film, the substantially liquid metal of the deformable thin film is configured to electro-mechanically couple a carrier and a socket base. Another embodiment includes a method of forming a LGA cartridge structure. The method includes: providing a deformable thin film having a first surface and a second surface, and forming at least one aperture within the deformable thin film through the first surface and the second surface, wherein the aperture is configured to hold a substantially liquid metal.Type: ApplicationFiled: January 21, 2013Publication date: July 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erwin B. Cohen, Mark C. H. Lamorey
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Patent number: 8759977Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.Type: GrantFiled: April 30, 2012Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 8756546Abstract: A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.Type: GrantFiled: July 25, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Erwin B. Cohen, Mark C. H. Lamorey, Marek A. Orlowski, Douglas O. Powell, David L. Questad, David B. Stone, Paul R. Walling
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NORMALLY CLOSED MICROELECTROMECHANICAL SWITCHES (MEMS), METHODS OF MANUFACTURE AND DESIGN STRUCTURES
Publication number: 20140070340Abstract: Normally closed (shut) micro-electro-mechanical switches (MEMS), methods of manufacture and design structures are provided. A structure includes a beam structure that includes a first end hinged on a first electrode and in electrical contact with a second electrode, in its natural state when not actuated.Type: ApplicationFiled: November 15, 2013Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dawn D. HALL, Mark C.H. LAMOREY, Anthony K. STAMPER -
Patent number: 8650512Abstract: Computer-implemented methods are disclosed for providing an elastic modulus map of an integrated circuit (IC) chip of a chip/device package, for identifying a probable failure site of the chip/device package from the elastic modulus map of the IC chip, for modifying a connector footprint of the chip/device package based on identifying a probable failure site from the elastic modulus map of the IC chip, and for modifying the IC chip based on identifying a probable failure from the elastic modulus map of the IC chip. Each layer of the IC chip may be mapped, and each grid shape of the mapped layers may comprise a metal area and a dielectric area. Grid shapes from each layer of the IC are vertically aligned to provide a combined spring constant for each grid shape, which are then mapped onto the elastic modulus map to identify possible failure sites in the chip/device package.Type: GrantFiled: November 15, 2012Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Mark C. H. Lamorey, Xiao Hu Liu, Thomas M. Shaw, Thomas A. Wassick
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Publication number: 20140033148Abstract: A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.Type: ApplicationFiled: July 25, 2012Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Erwin B. Cohen, Mark C.H. Lamorey, Marek A. Orlowski, Douglas O. Powell, David L. Questad, David B. Stone, Paul R. Walling
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Patent number: 8635765Abstract: A method of forming a micro-electrical-mechanical structure (MEMS), includes forming a plurality of electrodes on a substrate, forming a beam structure in electrical contact with a first of the electrodes, and bending the beam structure with a thermal process. The method further includes forming a cantilevered electrode extending over an end of the bent beam structure, and returning the beam structure to its original position, which will contact the cantilevered electrode in a normally closed position.Type: GrantFiled: June 15, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Dawn D. Hall, Mark C. H. Lamorey, Anthony K. Stamper
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Publication number: 20140021616Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.Type: ApplicationFiled: July 19, 2012Publication date: January 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diego Anzola, Evan G. Colgan, Kevin K. Dezfulian, Daniel C. Edelstein, Mark C. H. Lamorey, Sampath Purushothaman, Thomas M. Shaw, Roy R. Yu
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Publication number: 20140024146Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.Type: ApplicationFiled: August 3, 2012Publication date: January 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diego Anzola, Evan G. Colgan, Kevin K. Dezfulian, Daniel C. Edelstein, Mark C. H. Lamorey, Sampath Purushothaman, Thomas M. Shaw, Roy R. Yu
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Publication number: 20140021622Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: international Business Machines CorporationInventors: Griselda Bonilla, Timothy H. Daubenspeck, Mark C.H. Lamorey, Howard S. Landis, Xiao Hu Liu, David L. Questad, Thomas M. Shaw, David B. Stone
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Publication number: 20130285251Abstract: An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: International Business Machines CorporationInventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone