Patents by Inventor Mark Capellaro

Mark Capellaro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-mode forward error correction
    Patent number: 8296630
    Abstract: According to one embodiment, a system for multi-mode forward error correction comprises a substrate, forward error correction (FEC) modules, and a controller. The FEC modules are disposed outwardly from the substrate. A first FEC module performs forward error correction according to a first FEC scheme, and a second FEC module performs forward error correction according to a second FEC scheme. The controller configures the first FEC module and the second FEC module to convert from an input FEC scheme to an output FEC scheme for a stream.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: October 23, 2012
    Assignee: Fujitsu Limited
    Inventors: Arturo Garcia, Mark Capellaro, Steven R. Paul
  • FPGA configuration protection and control using hardware watchdog timer
    Patent number: 7971051
    Abstract: An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices. An apparatus for FPGA configuration protection comprises watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured and watchdog circuitry configured to receive the watchdog signal and to initiate reconfiguration of the FPGA if the watchdog signal is not received for or within a predetermined time. The circuitry in the FPGA may be configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Limited
    Inventors: Steven Paul, Arturo Garcia, Mark Capellaro
  • Multi-Mode Forward Error Correction
    Publication number: 20100088577
    Abstract: According to one embodiment, a system for multi-mode forward error correction comprises a substrate, forward error correction (FEC) modules, and a controller. The FEC modules are disposed outwardly from the substrate. A first FEC module performs forward error correction according to a first FEC scheme, and a second FEC module performs forward error correction according to a second FEC scheme. The controller configures the first FEC module and the second FEC module to convert from an input FEC scheme to an output FEC scheme for a stream.
    Type: Application
    Filed: February 9, 2009
    Publication date: April 8, 2010
    Applicant: Fujitsu Network Communications, Inc.
    Inventors: Arturo Garcia, Mark Capellaro, Steven R. Paul
  • FPGA configuration protection and control using hardware watchdog timer
    Publication number: 20090085603
    Abstract: An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices. An apparatus for FPGA configuration protection comprises watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured and watchdog circuitry configured to receive the watchdog signal and to initiate reconfiguration of the FPGA if the watchdog signal is not received for or within a predetermined time. The circuitry in the FPGA may be configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Steven Paul, Arturo Garcia, Mark Capellaro