Abstract: A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a SMAL regulator in which the amplifier sets load voltage with an envelope tracking bandwidth, and the switched converter is configured for current assist, and (b) a Switched Mode Power Supply configuration in which the amplifier is switch-decoupled, and the switcher circuit is switched configured with an output capacitor, operable as an SMPS providing load voltage with an adaptive tracking bandwidth that is less than the envelope tracking bandwidth.

Abstract: A single-person chair includes a proximal end and a distal end. A generally convex central portion extends between the proximal end and the distal end. The central portion extends upwardly, forming a first pool between the proximal end and the central portion and a second pool between the distal end and the central portion. A longitudinal centerline extends between the proximal end and the distal end. A first sidewall extends between the proximal end and the distal end on a first side of the longitudinal centerline. A second sidewall extends between the proximal end and the distal end on a second side of the longitudinal centerline such that that a liquid can be contained within the chair between the proximal end, the distal end, the first sidewall, and the second sidewall.

Abstract: A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a SMAL regulator in which the amplifier sets toad voltage with an envelope tracking bandwidth, and the switched converter is configured for current assist, and (b) a Switched Mode Power Supply configuration in which the amplifier is switch-decoupled, and the switcher circuit is switched configured with an output capacitor, operable as an SMPS providing load voltage with an adaptive tracking bandwidth that is less than the envelope tracking bandwidth.

Abstract: An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency FP and a secondary clock having a frequency FS?. The primary data is received over a fixed periodic interval TI and at a rate substantially equal to FP. The amount of primary data received over TI is known to be N. The data relay stage is further configurable to provide secondary data via a secondary data interface based on the primary data and the secondary clock. The circuit also includes a phase-locked loop (PLL) circuit configurable to receive an interval reference signal having a frequency FI substantially equal to 1/TI. The PLL circuit is also configurable to provide the secondary clock based on the interval reference signal.

Abstract: A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

Abstract: A method and system for digitally scaling a waveform. A method is described performing a linear waveform transformation and translation of a curve in a smooth and continuous fashion. Another method is described for scaling a waveform in which the available accuracy and resolution is manipulated for a given waveform. Specifically, by strategically placing virtual tap points of a waveform, as well as changing the scaling factors used for calculating points on the waveform provides for adjusting the accuracy and resolution in one or more regions of a waveform. These scaling methods provide a digital equivalent of a voltage tap-based analog resistor ladder used for digital-to-analog conversion. The digital virtual tap points represent the analog voltage tap points, and the vertical translation of the curve acts in a smooth, monotonic, and continuous fashion.

Abstract: Various technologies for efficiently storing and retrieving streaming data are described. Bits of data (e.g., P bits of data) are received and separated into most significant bits (MSB) of data and least significant bits (LSB) of data. Further, the MSB of data and the LSB of data are respectively packed into a first word and a second word. The first word is stored in a first area of a frame buffer and the second word is stored in a second area of the frame buffer. As a result, data is managed in a more efficient way to reduce memory bandwidth requirement.

Abstract: A method of operating a display includes operating a pixel of the display using a first signal to provide a first brightness level. A characteristic of the first signal is represented by a value in a range extending from a minimum signal value to a maximum signal value. A second brightness level is then selected and is different from the first brightness level. A truncated table is consulted and contains overdrive values for selected pairs of possible first and second brightness levels. The overdrive values are in a range extending from a minimum table value to a maximum table value, where the minimum table value is less than the minimum signal value or the maximum table value is greater than the maximum signal value or both. An overdrive signal is determined from the overdrive values of the truncated table based on the first and second brightness levels. The pixel is briefly operated using the overdrive signal to facilitate transition to the second brightness level.

Abstract: An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency FP and a secondary clock having a frequency FS?. The primary data is received over a fixed periodic interval TI and at a rate substantially equal to FP. The amount of primary data received over TI is known to be N. The data relay stage is further configurable to provide secondary data via a secondary data interface based on the primary data and the secondary clock. The circuit also includes a phase-locked loop (PLL) circuit configurable to receive an interval reference signal having a frequency FI substantially equal to 1/TI. The PLL circuit is also configurable to provide the secondary clock based on the interval reference signal.

Abstract: Various technologies for efficiently storing and retrieving streaming data are described. Bits of data (e.g., P bits of data) are received and separated into most significant bits (MSB) of data and least significant bits (LSB) of data. Further, the MSB of data and the LSB of data are respectively packed into a first word and a second word. The first word is stored in a first area of a frame buffer and the second word is stored in a second area of the frame buffer. As a result, data is managed in a more efficient way to reduce memory bandwidth requirement.

Abstract: A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

Abstract: An exemplary point-to-point display system comprises a host system, a timing controller, and a display. The host system is configured to provide data for display. The timing controller is configurable to provide data swapping, bus swapping, bit swapping, and combinations thereof to provide arranged data in response to the provided data. The display is configured to display the arranged data.

Abstract: A method and circuit capable of handling skew between a clock and data signal up to +/? one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.

Abstract: A method and system for digitally scaling a waveform. A method is described performing a linear waveform transformation and translation of a curve in a smooth and continuous fashion. Another method is described for scaling a waveform in which the available accuracy and resolution is manipulated for a given waveform. Specifically, by strategically placing virtual tap points of a waveform, as well as changing the scaling factors used for calculating points on the waveform provides for adjusting the accuracy and resolution in one or more regions of a waveform. These scaling methods provide a digital equivalent of a voltage tap-based analog resistor ladder used for digital-to-analog conversion. The digital virtual tap points represent the analog voltage tap points, and the vertical translation of the curve acts in a smooth, monotonic, and continuous fashion.

Abstract: A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed relative to the input clock signal. The clock phases are used to sample data from a data line. The sampled data is checked against a preamble pattern (a sequence of known data). A digital deskew control block selects one of the clock phases after analyzing the results of preamble pattern check such that subsequently received data is sampled with the appropriately selected clock phase.

Abstract: A recessible electrical receptacle including an open-ended housing mounted in a building member with a hinged closure pivotable from a service position to a recessed position flush with the building member. Sealing is disposed between the housing and closure for deterring introduction of fluid in the housing. A conventional duplex receptacle is mounted on the closure. Electrical conduits provide electrical communication between the receptacle and electrical contacts on the housing. A latch mounted on the housing may be selectively engaged with the housing to maintain the closure in the recessed position.