Abstract: Systems and methods for inter-kernel communication using one or more semiconductor devices. The semi-conductor devices include a kernel. The kernel may be in an inactive state unless performing an operation. One kernel of a first device may monitor data for an event. Once an event has occurred, the kernel sends an indication to a first inter-kernel communication circuitry. The inter-kernel communication circuitry determines an activation function of a plurality of activation functions is to be generated, generates the activation function, and transmits the activation function to a second kernel of a second device to waken and perform a function using a peer-to-peer connection.

Abstract: A fault-tolerant computer system includes first and second central processing units (CPUs) producing essentially identical data output streams, a voter delay buffer having a first FIFO buffer and a second FIFO buffer, and an I/O module connected to the CPUs. The I/O module includes a comparator for bitwise comparing the CPU data output streams. The first CPU data output stream is transmitted to peripheral devices if both CPU outputs remain substantially identical. Otherwise, if the comparator indicates differences, queued first and second CPU data are routed to the first and second FIFOs respectively, and subsequent data are retained in respective CPU buffers. While the CPUs continue processing, ongoing diagnostic procedures attempt to identify one or the other of the CPUs as malfunctioning and the remaining CPU as correctly-functioning. If the resulting diagnosis is inconclusive, the CPU having the lower rate of error correction is identified as being correctly-functioning.

Abstract: The inventive system essentially hides redundant paths to the peripheral devices from the operating system, by reporting a single “virtual” path to the peripheral busses over PCI bus 0. The virtual path includes at least a virtual peripheral bus controller and a virtual video controller. The system also tells the operating system that the real controllers are on another PCI bus on an opposite side of a PCI-to-PCI bridge connected also to PCI bus 0. An I/O system manager selects one of the actual paths, which may, but need not, be connected to PCI bus 0, to handle communications with the peripheral devices. The I/O system manager maintains the controllers on the unselected path in an off-line or standby mode, in case of a failure of one or more of the controllers on the selected path. If a failure occurs, the I/O system manager performs a fail-over operation to change the selection of controllers, and the peripheral devices continue to operate in the same manner on the peripheral busses.

Abstract: The inventive system includes an I/O subsystem that controls the synchronization of an off-line CPU to an on-line CPU, such that much of the synchronization operation takes place essentially as a background task for the on-line CPU. The I/O subsystem requests that the on-line CPU provide certain register and memory state information to general purpose registers on an I/O board. The I/O subsystem then provides the register contents to general purpose registers on the off-line CPU board, and the off-line CPU uses the information to set the states of certain of its registers and memory. The I/O system further includes a DMA engine that, at a time set by the I/O subsystem, copies pages of memory from the on-line CPU to the off-line CPU. At the end of the synchronization operation, the off-line CPU is directed to write to a predetermined register on the I/O board. When the off-line CPU performs the write operation, it indicates that the off-line CPU is in a known state and ready to go on-line.

Abstract: A digital data processing device includes a bus for transmitting signals (e.g., data and/or address information) between plural functional units (e.g., a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to the bus complementary portions of like information signals (e.g., longwords containing data). A fault detection element reads the resultant signal from the bus and compares it with at least portions of the corresponding signals originally generated by the processing sections themselves. If there is discrepancy, the fault-detector signals a fault, e.g., causing the unit to be taken off-line. By use of a redundant unit, processing can continue for fault-tolerant operation.

Abstract: A digital data processing device includes a bus for transmitting signals (e.g., data and/or address information) between plural functional units (e.g., a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to the bus complementary portions of like information signals (e.g., longwords containing data). A fault detection element reads the resultant signal from the bus and compares it with at least portions of the corresponding signals originally generated by the processing sections themselves. If there is discrepancy, the fault-detector signals a fault, e.g., causing the unit to be taken off-line. By use of a redundant unit, processing can continue for fault-tolerant operation.

Abstract: A bus device (10) the communicates with other bus devices (12, 13) on a communication channel (14) that includes a plurality of duplicated information buses (16, 17) selectively assumes bus-selection states in which it uses information from one or the other of the buses (16, 17). It also monitors the buses (16, 17) for errors in the information that the buses (16, 17) carry, and it broadcasts an error signal over other lines (18) of the communications channel (14) in response to detection of such an error, but only if an error occurs in information on the bus that its current bus-selection state designates. On the other hand, when an error-broadcast signal indicating an error on either bus in the information transmitted by that device (10) appears on the bus, that bus device (10) retransmits the information, regardless of that device's current bus-selection state. Inconsistent operation phasing among bus devices that have assumed different bus-selection states is thereby avoided.