Patents by Inventor Mark Donald Hill
Mark Donald Hill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9158704Abstract: A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses.Type: GrantFiled: January 24, 2013Date of Patent: October 13, 2015Assignee: Wisconsin Alumni Research FoundationInventors: Arkaprava Basu, Mark Donald Hill, Michael Mansfield Swift
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Publication number: 20140208064Abstract: A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses.Type: ApplicationFiled: January 24, 2013Publication date: July 24, 2014Applicant: Wisconsin Alumni Research FoundationInventors: Arkaprava Basu, Mark Donald Hill, Michael Mansfield Swift
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Patent number: 6981097Abstract: A cache coherence mechanism for a shared memory computer architecture employs tokens to designate a particular node's rights with respect to writing or reading a block of shared memory. The token system provides a correctness substrate to which a number of performance protocols may be freely added.Type: GrantFiled: March 14, 2003Date of Patent: December 27, 2005Assignee: Wisconsin Alumni Research FoundationInventors: Milo M. K. Martin, Mark Donald Hill, David Allen Wood
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Patent number: 6826671Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.Type: GrantFiled: October 9, 2001Date of Patent: November 30, 2004Assignee: Sun Microsystems, Inc.Inventors: Boris Ostrovsky, Daniel R. Cassiday, John R. Feehrer, David A. Wood, Pazhani Pillai, Christopher J. Jackson, Mark Donald Hill
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Publication number: 20040181636Abstract: A cache coherence mechanism for a shared memory computer architecture employs tokens to designate a particular node's rights with respect to writing or reading a block of shared memory. The token system provides a correctness substrate to which a number of performance protocols may be freely added.Type: ApplicationFiled: March 14, 2003Publication date: September 16, 2004Inventors: Milo M.K. Martin, Mark Donald Hill, David Allen Wood
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Patent number: 6574659Abstract: A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block.Type: GrantFiled: March 20, 2000Date of Patent: June 3, 2003Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill
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Publication number: 20030070058Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.Type: ApplicationFiled: October 9, 2001Publication date: April 10, 2003Inventors: Boris Ostrovsky, Daniel R. Cassiday, John R. Feehrer, David A. Wood, Pazhani Pillai, Christopher J. Jackson, Mark Donald Hill
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Patent number: 6496854Abstract: A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol.Type: GrantFiled: February 25, 2000Date of Patent: December 17, 2002Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill
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Patent number: 6377980Abstract: A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block.Type: GrantFiled: January 25, 1999Date of Patent: April 23, 2002Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill
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Patent number: 6243742Abstract: A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. The method includes the step of ascertaining whether the memory block is currently cached in the partial directory cache. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol.Type: GrantFiled: January 25, 1999Date of Patent: June 5, 2001Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill
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Patent number: 5940860Abstract: An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and the common bus both employ a common protocol and irrespective whether the external device and the common bus both operate at the same speed. Each of the memory blocks has a local physical address at a memory module of the computer node and an associated memory tag (Mtag) for tracking a state associated with that memory block, including a state for indicating whether that memory block is exclusive to the computer node, a state for indicating whether that memory block is shared by the computer node with the external device, and a state for indicating whether that memory block is invalid in the computer node. The apparatus includes receiver logic configured to receive, when coupled to the common bus of the computers node, memory access requests specific to the apparatus on the common bus.Type: GrantFiled: July 1, 1996Date of Patent: August 17, 1999Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill, David A. Wood
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Patent number: 5873117Abstract: A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block.Type: GrantFiled: July 1, 1996Date of Patent: February 16, 1999Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill
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Patent number: 5864671Abstract: A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. The method includes the step of ascertaining whether the memory block is currently cached in the partial directory cache. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol.Type: GrantFiled: July 1, 1996Date of Patent: January 26, 1999Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill
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Patent number: 5860109Abstract: An apparatus for facilitating the sharing of memory blocks, which has local physical addresses at a computer node, between the computer node and an external device. The apparatus includes snooping logic configured for coupling with a common bus of the computer node. The snooping logic is configured to monitor, when coupled to the common bus, memory access requests on the common bus. There is also included a snoop tag array coupled to the snooping logic. The snoop tag array includes tags for tracking all copies of a first plurality of memory blocks of the memory blocks cached by the external device. Further, there is included a protocol transformer logic coupled to the snooping logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device.Type: GrantFiled: July 1, 1996Date of Patent: January 12, 1999Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill, David A. Wood
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Patent number: 5835906Abstract: A method, in a computer system having a first plurality of stored data objects and capable of running multiple threads concurrently, for preventing access conflicts. The method includes the step of providing a dynamic lock structure having a plurality of dynamic lock structure members. There is also the step of mapping a second plurality of stored data objects of the first plurality of stored data objects into a first dynamic lock structure member of the plurality of dynamic lock structure members in accordance with a mapping function. Due to the mapping function, the plurality of dynamic lock structure members become fewer in number than the number of the first plurality of stored data objects. The first dynamic lock structure member is configured to store identities of a third plurality of stored data objects.Type: GrantFiled: July 1, 1996Date of Patent: November 10, 1998Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill
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Patent number: 5829034Abstract: A coherence transformer for allowing a computer node and one or more external devices to share memory blocks having local physical addresses at a memory module of the computer node. The coherence transformer includes logic for ascertaining whether a memory access request from the external device for a memory block should be responded to using a snoop-only approach or an Mtag-only approach. The snoop-only approach requires a tag in a snoop tag array of the coherence transformer be available to track the memory block for an entire duration that the memory block is cached by the external device. The Mtag-only approach only temporarily stores the memory block until a global state associated with the memory block can be written back into the memory module of the computer node. The snoop tag array allows the coherence transformer to snoop the bus of the computer node to intervene and respond to memory access requests pertaining to a memory block externally cached and tracked by the snoop tag array.Type: GrantFiled: July 1, 1996Date of Patent: October 27, 1998Assignee: Sun Microsystems, Inc.Inventors: Erik E. Hagersten, Mark Donald Hill, David A. Wood