Abstract: A system for acquiring environmental information measurements. The 5 system (100) utilize a sensor, (205) a front-end circuit, (310) a loop filter (315), a switch controller (206), and a reduced-order loop control circuit to provide reliable data measurements while providing robust system behavior. The system further includes a sensor simulator (330) for simulating the operation of the sensor (205) and testing the operation of the front-end circuit (310) and the loop filter (315).

Abstract: A method and apparatus for measuring and compensating for stray capacitance of a micro-machined sensor of an accelerometer system is disclosed. Stray capacitance differences between a top plate and a sensing element and between a bottom plate and the sensing element degrade accelerometer performance if not compensated for. Measurement of stray capacitance difference is achieved by operating the accelerometer in two calibration phases and measuring the steady-state output voltage in each of the two phases. In calibration phase 1, no force is applied to the sensor during clock intervals 1-4. In calibration phase 2, a dummy force up is applied and then a dummy force down is applied during those intervals 1-4. The difference in the output voltage of the two calibration phases is representative of the difference in stray capacitance of the sensor. Capacitance is added to the top or bottom plates in an amount proportional to the measured stray capacitance.

Abstract: An NDIRTY cache line lookahead technique is used to expedite cache flush and export operations by providing a mechanism to avoid scanning at least some cache lines that do not contain dirty data (and therefore will not have to be exported). The exemplary cache organization uses one-line lookahead where each cache line but the last has associated with it an NDIRTY bit that indicates whether the next cache line contains dirty data. For cache flush and export operations, when a cache line (N) is read to check for dirty data that must be exported, the NDIRTY bit for that cache line is also tested to determine whether the next cache line (N+1) contains dirty data--if the NDIRTY bit is clear, indicating that the next cache line is clean, then that line is skipped and the scan proceeds with the line after that (N+2). This exemplary one-line lookahead implementation is readily extendible to N-line lookahead.

Abstract: A pre-charge load device to pre-charge an input on a sense amplifier is coupled between a positive voltage rail and the input to the sense amplifier and is biased by a bias network coupled between the positive voltage rail and the sense amplifier input to adapt the sense amplifier slew rate in relation to large or unpredictable capacitive impedance changes on the sense amplifier input.

Abstract: A current source suitable for use as a loop filter in a phase-locked loop having two aspects of automatic gain control one for prohibiting the voltage controlled oscillator from stopping as the input voltage approaches the limits of the oscillator and another to compensate for current limiting drain to source voltage drops.

Abstract: A fully differential voltage controlled oscillator having a large common mode rejection ratio is disclosed with a first and a second phase detector disposed between the output of a differential comparator and the input of a differential triangle wave generator to insure 180 degree out of phase operation.

Abstract: A signed arithmetic data processing system (20) detects a multiply (MUL) or a multiply-and-accumulate (MAC) instruction in which a multiplier and a multiplicand each assume their respective maximum negative values. If one or both of the operands is not equal to its maximum negative value, the multiplication proceeds normally, such as in a modified Booth's multiplier/MAC (33). However, if both operands are equal to their respective maximum negative values, the data processing system (20) substitutes a maximum positive constant for the output of the multiplier/MAC (33). This substitution allows the result to be expressed with one fewer bits. The resulting error is very small and becomes insignificant in most digital signal processing algorithms, especially those based on fractional, saturation arithmetic. Alternatively, an extra bit of precision may be achieved for a given hardware size.