Abstract: Computer algorithms design to execute on a computer system embedded inside a starter or deep cycle battery that calculate optimal charge rates and detect internal alarm conditions and make this information externally available.

Abstract: A computer system embedded inside a starter or deep cycle battery that includes manufacturing data, the means to monitor battery pressure, the means to monitor electrolyte level and the means to transfer information to an external device.

Abstract: Boot up instructions may be stored on a memory coupled to the peripheral component interconnect (PCI) bus. These instructions may be accessed, despite the fact that peripheral component interconnect devices are normally not active during the boot up sequence. As a result, both the basic input/output system and other information may be stored on a reprogrammable memory coupled to the PCI bus. In some embodiments, this may reduce costs by avoiding the need for two semiconductor memories, one on the PCI bus and the other on a legacy bus.

Abstract: Boot up instructions may be stored on a memory coupled to the peripheral component interconnect (PCI) bus. These instructions may be accessed, despite the fact that peripheral component interconnect devices are normally not active during the boot up sequence. As a result, both the basic input/output system and other information may be stored on a reprogrammable memory coupled to the PCI bus. In some embodiments, this may reduce costs by avoiding the need for two semiconductor memories, one on the PCI bus and the other on a legacy bus.

Abstract: Boot up instructions may be stored on a memory coupled to the peripheral component interconnect (PCI) bus. These instructions may be accessed, despite the fact that peripheral component interconnect devices are normally not active during the boot up sequence. As a result, both the basic input/output system and other information may be stored on a reprogrammable memory coupled to the PCI bus. In some embodiments, this may reduce costs by avoiding the need for two semiconductor memories, one on the PCI bus and the other on a legacy bus.

Abstract: According to embodiments of the invention, multiple memory bus masters of a computer board are connected via transmission lines to a common node. The common node is further connected to a memory array. Each memory bus master can drive clock signals to the memory array. An isolation circuit is placed between the transmission lines and the common node. The isolation circuit is controllable to select one of the memory bus masters to drive clock signals to the memory array, while isolating the transmission lines of the other bus masters from the common node to reduce clock signal corruption.

Abstract: A method to combine diversely encoded data streams includes receiving a first data stream in a first encoded format, decoding the first data stream into a decoded format, obtaining a second data stream in the decoded format, and combining the decoded first data stream with the second data stream. The first encoded format may, for example, be associated with a video data stream, an audio data stream, or a multimedia data stream. The decoded format may be any format which allows two data streams to be combined in a substantially direct manner such as, for example, a linear pulse code modulated (LPCM) data format.