Patents by Inventor Mark Edward Gibson
Mark Edward Gibson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10833174Abstract: A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.Type: GrantFiled: October 26, 2018Date of Patent: November 10, 2020Assignee: NXP USA, INC.Inventors: Bernhard Grote, Ljubo Radic, Saumitra Raj Mehrotra, Tania Tricia-Marie Thomas, Mark Edward Gibson
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Patent number: 10811502Abstract: A method for manufacturing a super-junction MOSFET entails forming a recessed shield electrode in a trench in a semiconductor layer of a substrate, the trench being lined with a first oxide layer. When the electrically conductive material forming the shield electrode is removed to recess the shield electrode, the first oxide layer on sidewalls of the trench is exposed. Removal of the first oxide layer from the sidewalls and from shield sidewalls of the electrode produces openings at a top part of the shield sidewalls. A second oxide layer is formed over the shield electrode and fills the openings. Part of the second oxide layer is removed to expose a top surface of the shield electrode. A gate dielectric is formed over the top surface of the shield electrode and conductive material is deposited over the gate dielectric in the trench to form a gate electrode of the MOSFET.Type: GrantFiled: May 30, 2019Date of Patent: October 20, 2020Assignee: NXP USA, Inc.Inventors: Vishnu Khemka, Tanuj Saxena, Ganming Qin, Raghuveer Vankayala Gupta, Mark Edward Gibson, Moaniss Zitouni
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Publication number: 20200152786Abstract: A vertical bi-directional device includes first and second conductive gates in a semiconductor layer with a first vertical gate oxide on a sidewall of the first conductive gate and a second vertical gate oxide on a sidewall of the second conductive gate. A first heavily doped region of a first conductivity type is at the surface adjacent the first conductive gate, and a second heavily doped region of the first conductive type is at the surface adjacent to the second conductive gate. Doped regions of the first conductivity type extend below the conductive gates towards a substrate. A doped region of a second conductivity type extends laterally from the first vertical gate oxide to the second vertical gate oxide, and a heavily doped region of the second conductivity type is at the surface of the semiconductor layer, between the first and second heavily doped regions of the first conductivity type.Type: ApplicationFiled: November 13, 2018Publication date: May 14, 2020Inventors: Moaniss ZITOUNI, Vishnu KHEMKA, Ganming QIN, Tanuj SAXENA, Raghuveer Vankayala GUPTA, Mark Edward GIBSON
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Patent number: 10644146Abstract: A vertical bi-directional device includes first and second conductive gates in a semiconductor layer with a first vertical gate oxide on a sidewall of the first conductive gate and a second vertical gate oxide on a sidewall of the second conductive gate. A first heavily doped region of a first conductivity type is at the surface adjacent the first conductive gate, and a second heavily doped region of the first conductive type is at the surface adjacent to the second conductive gate. Doped regions of the first conductivity type extend below the conductive gates towards a substrate. A doped region of a second conductivity type extends laterally from the first vertical gate oxide to the second vertical gate oxide, and a heavily doped region of the second conductivity type is at the surface of the semiconductor layer, between the first and second heavily doped regions of the first conductivity type.Type: GrantFiled: November 13, 2018Date of Patent: May 5, 2020Assignee: NXP USA, Inc.Inventors: Moaniss Zitouni, Vishnu Khemka, Ganming Qin, Tanuj Saxena, Raghuveer Vankayala Gupta, Mark Edward Gibson
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Publication number: 20200135896Abstract: A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Bernhard Grote, Ljubo Radic, Saumitra Raj Mehrotra, Tania Tricia-Marie Thomas, Mark Edward Gibson
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Publication number: 20200098912Abstract: A transistor device includes a conductive structure located in a trench of semiconductor material. The conductive structure is located closer to a first sidewall of the trench than to a second sidewall of the trench. The conductive structure serves as a control terminal and a field plate for a transistor. At a first location in the trench where the conductive structure functions as a control terminal for a transistor, the conductive structure is located a first lateral distance from the trench sidewall with dielectric located in between. At a second location in the trench where the conductive structure functions as a field plate, the conductive structure is located a second lateral distance from the trench sidewall with dielectric located in between. The second lateral distance is greater than the first lateral distance.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: BERNHARD GROTE, Ljubo Radic, Saumitra Raj Mehrotra, Tania Tricia-Marie Thomas, Mark Edward Gibson
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Patent number: 10600911Abstract: A transistor includes a trench formed in a semiconductor substrate. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to a first sidewall of the trench. A first field plate is formed in the trench with the first field plate located between a second edge of the gate electrode and a second sidewall of the trench. A dielectric material is formed in the trench with the dielectric material having a first thickness between the first sidewall and a first edge of the first field plate, and a second thickness between the second sidewall and a second edge of the first field plate, the second thickness larger than the first thickness.Type: GrantFiled: September 26, 2017Date of Patent: March 24, 2020Assignee: NXP USA, INC.Inventors: Bernhard Grote, Saumitra Raj Mehrotra, Ljubo Radic, Vishnu Khemka, Mark Edward Gibson
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Publication number: 20190097045Abstract: A transistor includes a trench formed in a semiconductor substrate. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to a first sidewall of the trench. A first field plate is formed in the trench with the first field plate located between a second edge of the gate electrode and a second sidewall of the trench. A dielectric material is formed in the trench with the dielectric material having a first thickness between the first sidewall and a first edge of the first field plate, and a second thickness between the second sidewall and a second edge of the first field plate, the second thickness larger than the first thickness.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: BERNHARD GROTE, SAUMITRA RAJ MEHROTRA, LJUBO RADIC, VISHNU KHEMKA, MARK EDWARD GIBSON
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Patent number: 10153357Abstract: A method for manufacturing a super junction power MOSFET includes forming a first trench in a substrate, forming a first oxide layer over the substrate and in the bottom and along sidewalls of the trench, depositing electrically conductive material in the trench, masking a first portion of the electrically conductive material, forming a recessed portion of the electrically conductive material, forming an oxide portion over and in contact with the recessed portion of the electrically conductive material, removing a part of the oxide portion by masking, removing the first oxide layer on the sidewalls while another part of the oxide portion remains in contact with the recessed portion of the electrically conductive material, forming a gate dielectric along exposed sidewalls of the trench, and depositing additional electrically conductive material over the other part of the oxide portion in the trench.Type: GrantFiled: August 28, 2017Date of Patent: December 11, 2018Assignee: NXP USA, Inc.Inventors: Ganming Qin, Vishnu Khemka, Tanuj Saxena, Moaniss Zitouni, Raghuveer Vankayala Gupta, Mark Edward Gibson