Patents by Inventor Mark Edward Rossman

Mark Edward Rossman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs
    Patent number: 9817941
    Abstract: Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 14, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Mark Edward Rossman
  • Method and system for creating improved routing polygon abstracts
    Patent number: 9524364
    Abstract: Methods and systems for creating and implementing improved routing polygon abstracts that can be used to efficiently find areas to route through in electrical designs, where the routing polygon abstracts include at least a horizontal routing polygon abstract, a maximum horizontal routing polygon abstract, a vertical routing polygon abstract, and a maximum vertical routing polygon abstract, that are created through various steps including bloating, shrinking, merging, and extending the objects towards an outer boundary.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: December 20, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mark Edward Rossman, Sabra Alexis Wieditz Rossman
  • METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING HIGH CURRENT CARRYING INTERCONNECTS IN ELECTRONIC DESIGNS
    Publication number: 20160070841
    Abstract: Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 10, 2016
    Applicant: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Mark Edward Rossman