Patents by Inventor Mark F. Chadurjian

Mark F. Chadurjian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming dual height solder interconnections
    Patent number: 5251806
    Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.
    Type: Grant
    Filed: April 16, 1992
    Date of Patent: October 12, 1993
    Assignee: International Business Machines Corporation
    Inventors: Birendra N. Agarwala, Aziz M. Ahsan, Arthur Bross, Mark F. Chadurjian, Nicholas G. Koopman, Li-Chung Lee, Karl J. Puttlitz, Sudipta K. Ray, James G. Ryan, Joseph G. Schaefer, Kamalesh K. Srivastava, Paul A. Totta, Erick G. Walton, Adolf E. Wirsing
  • Solder mass having conductive encapsulating arrangement
    Patent number: 5130779
    Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.
    Type: Grant
    Filed: June 19, 1990
    Date of Patent: July 14, 1992
    Assignee: International Business Machines Corporation
    Inventors: Birendra N. Agarwala, Aziz M. Ahsan, Arthur Bross, Mark F. Chadurjian, Nicholas G. Koopman, Li-Chung Lee, Karl J. Puttlitz, Sudipta K. Ray, James G. Ryan, Joseph G. Schaefer, Kamalesh K. Srivastava, Paul A. Totta, Erick G. Walton, Adolf E. Wirsing