Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material.

Abstract: An interconnect module providing conductive interconnection paths between an integrated chip, a printed wiring board, and at least one layer within the module, incorporating a plurality of alternating dielectric and conductive layers laminated together to form a unitary structure. The module includes a chip attach surface and a board attach surface, that define contact pads for attachment to corresponding pads on the chip and printed wiring board, respectively, by means of solder balls.

Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Abstract: A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Abstract: A package for mounting an integrated circuit chip includes a body having at least a first region and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.

Abstract: A package for mounting an integrated circuit chip includes a body having at least a first region, the size of the integrated circuit chip, and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.

Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Abstract: The present invention relates to assembly techniques and the resulting products which are thermally stable, have high structural integrity, and compensate for thermal stresses that occur between the various components of the package. This is accomplished, in-part, by designing the package so that the coefficient of thermal expansion (CTE) of a stiffening ring which is mounted on the package substrate matches the CTE of the substrate and optional lid. Further, the particular adhesives used to bond the stiffening ring are chosen to match their CTE to that of the substrate, ring and lid. Moreover, the substrate is designed so that its CTE, at least in-part, matches that of the chip, and also that of the stiffening ring.

Abstract: A method of manufacturing a multi-layered structure includes forming first and second layers, patterning the first layer, determining a distribution of material in at least one area of the first layer, and altering the material content of one of the first and second layers in at least one of the first layer area and a corresponding area of the second layer to approximately match the material content of the first layer and second layers.

Abstract: A method of minimizing warp and die stress in the production of an electronic assembly includes connecting one surface of a die to a package, and connecting an opposite surface of the die to a lid disposed over a constraining ring that is mounted to the package. The lid has a size, shape and coefficient of thermal expansion (CTE) selected to generate a bending moment that opposes bending moments resulting from connecting the die to the package.

Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.

Abstract: A chip package is provided for controlling warp of electronic assemblies. The chip package has a first component mounted on one side of a substrate. The substrate is a multi-layered laminate having a plurality of dielectric layers made of an organic material. The first component has a different coefficient of thermal expansion (CTE) than the substrate. The chip package includes a second component mounted on an opposite side of the substrate in a location substantially opposite the first component. The second component has a CTE that approximately matches the CTE of the first component. The second component tends to generate bending moments that offset distorting bending moments that may otherwise exist in the chip package without the second component.

Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Abstract: A lid for a chip/package system includes a body sized to fit over an integrated circuit chip and being connectable to a package. The body has at least two regions exhibiting different coefficients of thermal expansion, with one CTE matching that of the chip and the other matching that of the package.

Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.

Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.

Abstract: A package for mounting an integrated circuit chip includes a body having at least a first region and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.